Jasmine Jhihan B. Clark

Array ( [id] => 10645372 [patent_doc_number] => 09362247 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-07 [patent_title] => 'Systems and methods for bonding semiconductor elements' [patent_app_type] => utility [patent_app_number] => 14/822164 [patent_app_country] => US [patent_app_date] => 2015-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 5274 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14822164 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11787598 [patent_doc_number] => 09397060 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-19 [patent_title] => 'Package on package structure' [patent_app_type] => utility [patent_app_number] => 14/819189 [patent_app_country] => US [patent_app_date] => 2015-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2062 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14819189 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10993151 [patent_doc_number] => 20160190097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/817502 [patent_app_country] => US [patent_app_date] => 2015-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3550 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14817502 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10689512 [patent_doc_number] => 20160035658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-04 [patent_title] => 'Encapsulated electronic chip device with mounting provision and externally accessible electric connection structure' [patent_app_type] => utility [patent_app_number] => 14/815367 [patent_app_country] => US [patent_app_date] => 2015-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5540 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14815367 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11781829 [patent_doc_number] => 09391028 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-07-12 [patent_title] => 'Integrated circuit dies having alignment marks and methods of forming same' [patent_app_type] => utility [patent_app_number] => 14/815603 [patent_app_country] => US [patent_app_date] => 2015-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 6579 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14815603 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11424919 [patent_doc_number] => 20170033065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-02 [patent_title] => 'Methods of Forming Connector Pad Structures, Interconnect Structures, and Structures Thereof' [patent_app_type] => utility [patent_app_number] => 14/815584 [patent_app_country] => US [patent_app_date] => 2015-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9158 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14815584 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11239934 [patent_doc_number] => 09466580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-11 [patent_title] => 'Semiconductor package and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 14/815435 [patent_app_country] => US [patent_app_date] => 2015-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5908 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14815435 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10635465 [patent_doc_number] => 09352957 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-31 [patent_title] => 'Semiconductor device, related manufacturing method, and related electronic device' [patent_app_type] => utility [patent_app_number] => 14/809642 [patent_app_country] => US [patent_app_date] => 2015-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 6988 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14809642 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13653309 [patent_doc_number] => 09852975 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-26 [patent_title] => Wiring board, electronic device, and electronic module [patent_app_type] => utility [patent_app_number] => 15/322217 [patent_app_country] => US [patent_app_date] => 2015-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 10185 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15322217 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11765156 [patent_doc_number] => 09373605 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-06-21 [patent_title] => 'DIE packages and methods of manufacture thereof' [patent_app_type] => utility [patent_app_number] => 14/801277 [patent_app_country] => US [patent_app_date] => 2015-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 42 [patent_no_of_words] => 10560 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14801277 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10433379 [patent_doc_number] => 20150318391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-05 [patent_title] => 'SEMICONDUCTOR ELEMENT AND DISPLAY DEVICE USING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/801098 [patent_app_country] => US [patent_app_date] => 2015-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12322 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14801098 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11221568 [patent_doc_number] => 09449911 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-09-20 [patent_title] => 'Fan-out wafer level package and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 14/800990 [patent_app_country] => US [patent_app_date] => 2015-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 2846 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14800990 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10674026 [patent_doc_number] => 20160020171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-21 [patent_title] => 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/798833 [patent_app_country] => US [patent_app_date] => 2015-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3776 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14798833 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11214771 [patent_doc_number] => 09443811 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-13 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/799564 [patent_app_country] => US [patent_app_date] => 2015-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7249 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14799564 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10447992 [patent_doc_number] => 20150333005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-19 [patent_title] => 'PLACEMENT OF MONOLITHIC INTER-TIER VIAS (MIVs) WITHIN MONOLITHIC THREE DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) USING CLUSTERING TO INCREASE USABLE WHITESPAC' [patent_app_type] => utility [patent_app_number] => 14/795914 [patent_app_country] => US [patent_app_date] => 2015-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7233 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14795914 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10418115 [patent_doc_number] => 20150303125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'SEMICONDUCTOR APPARATUS INCLUDING A HEAT DISSIPATING MEMBER' [patent_app_type] => utility [patent_app_number] => 14/788853 [patent_app_country] => US [patent_app_date] => 2015-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 9756 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14788853 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11288277 [patent_doc_number] => 09504150 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-22 [patent_title] => 'Printed electronics' [patent_app_type] => utility [patent_app_number] => 14/751418 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 6363 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14751418 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14039133 [patent_doc_number] => 10231338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-12 [patent_title] => Methods of forming trenches in packages structures and structures formed thereby [patent_app_type] => utility [patent_app_number] => 14/748496 [patent_app_country] => US [patent_app_date] => 2015-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 3054 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14748496 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11036214 [patent_doc_number] => 20160233170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-11 [patent_title] => 'METHOD OF MANUFACTURING ELECTRONIC DEVICE AND ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 14/741853 [patent_app_country] => US [patent_app_date] => 2015-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4623 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14741853 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10689443 [patent_doc_number] => 20160035589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-04 [patent_title] => 'SEMICONDUCTOR DEVICE, RELATED MANUFACTURING METHOD, AND RELATED ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 14/738513 [patent_app_country] => US [patent_app_date] => 2015-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4088 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14738513 [rel_patent_id] =>[rel_patent_doc_number] =>)