Jasmine Jhihan B. Clark

Array ( [id] => 11590033 [patent_doc_number] => 20170114444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'METHOD FOR PRODUCING A COATING AND OPTOELECTRONIC SEMICONDUCTOR COMPONENT HAVING A COATING' [patent_app_type] => utility [patent_app_number] => 15/318330 [patent_app_country] => US [patent_app_date] => 2015-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8410 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15318330 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10733013 [patent_doc_number] => 20160079163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/727785 [patent_app_country] => US [patent_app_date] => 2015-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11097 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14727785 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10725630 [patent_doc_number] => 20160071778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-10 [patent_title] => 'Semiconductor Device and Manufacturing Method Thereof' [patent_app_type] => utility [patent_app_number] => 14/717309 [patent_app_country] => US [patent_app_date] => 2015-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7019 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14717309 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10765211 [patent_doc_number] => 20160111367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'POWER SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/712776 [patent_app_country] => US [patent_app_date] => 2015-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3347 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14712776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11346387 [patent_doc_number] => 09530803 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-27 [patent_title] => 'Electrical connection structure with via hole, array substrate and display device' [patent_app_type] => utility [patent_app_number] => 14/906443 [patent_app_country] => US [patent_app_date] => 2015-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 4114 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14906443 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10350888 [patent_doc_number] => 20150235894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-20 [patent_title] => 'Interconnect Structure and Method of Forming the Same' [patent_app_type] => utility [patent_app_number] => 14/705840 [patent_app_country] => US [patent_app_date] => 2015-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6193 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14705840 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10433220 [patent_doc_number] => 20150318232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-05 [patent_title] => 'METHOD AND APPARATUS FOR MOUNTING SOLDER BALLS TO AN EXPOSED PAD OR TERMINAL OF A SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/699496 [patent_app_country] => US [patent_app_date] => 2015-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2492 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14699496 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10463916 [patent_doc_number] => 20150348931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MAKING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/700060 [patent_app_country] => US [patent_app_date] => 2015-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7075 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14700060 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10787395 [patent_doc_number] => 20160133551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-12 [patent_title] => 'PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/695125 [patent_app_country] => US [patent_app_date] => 2015-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4362 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14695125 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11239918 [patent_doc_number] => 09466564 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-10-11 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 14/692762 [patent_app_country] => US [patent_app_date] => 2015-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3895 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14692762 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11187519 [patent_doc_number] => 09418929 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-16 [patent_title] => 'Integrated circuit with sewn interconnects' [patent_app_type] => utility [patent_app_number] => 14/692747 [patent_app_country] => US [patent_app_date] => 2015-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4432 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14692747 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13107431 [patent_doc_number] => 10072351 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-11 [patent_title] => Methods and apparati for making thin semi-conductor wafers with locally controlled regions that are relatively thicker than other regions and such wafers [patent_app_type] => utility [patent_app_number] => 15/306787 [patent_app_country] => US [patent_app_date] => 2015-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 47 [patent_no_of_words] => 26345 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15306787 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11110901 [patent_doc_number] => 20160307871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-20 [patent_title] => 'Fan-out POP Structure with Inconsecutive Polymer Layer' [patent_app_type] => utility [patent_app_number] => 14/690061 [patent_app_country] => US [patent_app_date] => 2015-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 4617 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14690061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11110902 [patent_doc_number] => 20160307872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-20 [patent_title] => 'Discrete Polymer in Fan-Out Packages' [patent_app_type] => utility [patent_app_number] => 14/690081 [patent_app_country] => US [patent_app_date] => 2015-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 5421 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14690081 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10610993 [patent_doc_number] => 09331036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-03 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/688953 [patent_app_country] => US [patent_app_date] => 2015-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 15274 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14688953 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11265914 [patent_doc_number] => 09490217 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-08 [patent_title] => 'Overlay marks and semiconductor process using the overlay marks' [patent_app_type] => utility [patent_app_number] => 14/687912 [patent_app_country] => US [patent_app_date] => 2015-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4007 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14687912 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11510258 [patent_doc_number] => 09601424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-21 [patent_title] => 'Interposer and methods of forming and testing an interposer' [patent_app_type] => utility [patent_app_number] => 14/684664 [patent_app_country] => US [patent_app_date] => 2015-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 2569 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14684664 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11103844 [patent_doc_number] => 20160300814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-13 [patent_title] => 'ELECTRONIC PACKAGE THAT INCLUDES A PLURALITY OF INTEGRATED CIRCUIT DEVICES BONDED IN A THREE-DIMENSIONAL STACK ARRANGEMENT' [patent_app_type] => utility [patent_app_number] => 14/685061 [patent_app_country] => US [patent_app_date] => 2015-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4568 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14685061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11239922 [patent_doc_number] => 09466568 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-11 [patent_title] => 'Distributed on-chip decoupling apparatus and method using package interconnect' [patent_app_type] => utility [patent_app_number] => 14/683073 [patent_app_country] => US [patent_app_date] => 2015-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3789 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14683073 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10597371 [patent_doc_number] => 09318465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-19 [patent_title] => 'Methods for forming a semiconductor device package' [patent_app_type] => utility [patent_app_number] => 14/681149 [patent_app_country] => US [patent_app_date] => 2015-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 5997 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14681149 [rel_patent_id] =>[rel_patent_doc_number] =>)