Search

Jasmine Jhihan B. Clark

Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )

Most Active Art Unit
2815
Art Unit(s)
2815, 2899, 3621, 2816, 2503
Total Applications
3065
Issued Applications
2831
Pending Applications
98
Abandoned Applications
163

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10125248 [patent_doc_number] => 09159614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-13 [patent_title] => 'Packaging substrate and method for manufacturing same' [patent_app_type] => utility [patent_app_number] => 14/140461 [patent_app_country] => US [patent_app_date] => 2013-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2528 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14140461 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/140461
Packaging substrate and method for manufacturing same Dec 23, 2013 Issued
Array ( [id] => 9844800 [patent_doc_number] => 08946718 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-03 [patent_title] => 'Semiconductor element and display device using the same' [patent_app_type] => utility [patent_app_number] => 14/133820 [patent_app_country] => US [patent_app_date] => 2013-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 49 [patent_no_of_words] => 12322 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14133820 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/133820
Semiconductor element and display device using the same Dec 18, 2013 Issued
Array ( [id] => 10004233 [patent_doc_number] => 09048332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-02 [patent_title] => 'Semiconductor device manufacturing method and semiconductor mounting substrate' [patent_app_type] => utility [patent_app_number] => 14/134289 [patent_app_country] => US [patent_app_date] => 2013-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 7013 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14134289 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/134289
Semiconductor device manufacturing method and semiconductor mounting substrate Dec 18, 2013 Issued
Array ( [id] => 10260146 [patent_doc_number] => 20150145143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'PLACEMENT OF MONOLITHIC INTER-TIER VIAS (MIVs) WITHIN MONOLITHIC THREE DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) USING CLUSTERING TO INCREASE USABLE WHITESPACE' [patent_app_type] => utility [patent_app_number] => 14/132098 [patent_app_country] => US [patent_app_date] => 2013-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7183 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14132098 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/132098
Placement of monolithic inter-tier vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespace Dec 17, 2013 Issued
Array ( [id] => 10286042 [patent_doc_number] => 20150171040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-18 [patent_title] => 'ELECTROPLATED SOLDER FOR HIGH-TEMPERATURE INTERCONNECT' [patent_app_type] => utility [patent_app_number] => 14/109616 [patent_app_country] => US [patent_app_date] => 2013-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4864 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14109616 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/109616
Electroplated solder for high-temperature interconnect Dec 16, 2013 Issued
Array ( [id] => 9393471 [patent_doc_number] => 20140090876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-03 [patent_title] => 'METHOD OF MOUNTING SEMICONDUCTOR CHIPS, SEMICONDUCTOR DEVICE OBTAINED USING THE METHOD, METHOD OF CONNECTING SEMICONDUCTOR CHIPS, THREE-DIMENSIONAL STRUCTURE IN WHICH WIRING IS PROVIDED ON ITS SURFACE, AND METHOD OF PRODUCING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/096504 [patent_app_country] => US [patent_app_date] => 2013-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 22434 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14096504 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/096504
Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same Dec 3, 2013 Issued
Array ( [id] => 11927431 [patent_doc_number] => 09795033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-17 [patent_title] => 'Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same' [patent_app_type] => utility [patent_app_number] => 14/096514 [patent_app_country] => US [patent_app_date] => 2013-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 48 [patent_no_of_words] => 22480 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14096514 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/096514
Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same Dec 3, 2013 Issued
Array ( [id] => 9488430 [patent_doc_number] => 20140138836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-22 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/081585 [patent_app_country] => US [patent_app_date] => 2013-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 15254 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14081585 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/081585
Semiconductor device Nov 14, 2013 Issued
Array ( [id] => 9861972 [patent_doc_number] => 20150041989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => 'SEMICONDUCTOR APPRATUS AND SEMICONDUCTOR SYSTEM USING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/081647 [patent_app_country] => US [patent_app_date] => 2013-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5797 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14081647 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/081647
Semiconductor apparatus and semiconductor system using the same Nov 14, 2013 Issued
Array ( [id] => 9360546 [patent_doc_number] => 20140070418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-13 [patent_title] => 'SEMICONDUCTOR INTERCONNECT STRUCTURE HAVING ENHANCED PERFORMANCE AND RELIABILITY' [patent_app_type] => utility [patent_app_number] => 14/080160 [patent_app_country] => US [patent_app_date] => 2013-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3481 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14080160 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/080160
Semiconductor interconnect structure having enhanced performance and reliability Nov 13, 2013 Issued
Array ( [id] => 10118662 [patent_doc_number] => 09153550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-06 [patent_title] => 'Substrate design with balanced metal and solder resist density' [patent_app_type] => utility [patent_app_number] => 14/080106 [patent_app_country] => US [patent_app_date] => 2013-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3922 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14080106 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/080106
Substrate design with balanced metal and solder resist density Nov 13, 2013 Issued
Array ( [id] => 9503381 [patent_doc_number] => 08741694 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-06-03 [patent_title] => 'Placing heat sink into packaging by strip formation assembly' [patent_app_type] => utility [patent_app_number] => 14/075987 [patent_app_country] => US [patent_app_date] => 2013-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3021 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14075987 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/075987
Placing heat sink into packaging by strip formation assembly Nov 7, 2013 Issued
Array ( [id] => 9335152 [patent_doc_number] => 20140061934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-06 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/075513 [patent_app_country] => US [patent_app_date] => 2013-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7228 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14075513 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/075513
Semiconductor device Nov 7, 2013 Issued
Array ( [id] => 10370414 [patent_doc_number] => 20150255419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'SEMICONDUCTOR DEVICE AND CERAMIC CIRCUIT SUBSTRATE, AND PRODUCING METHOD OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/433764 [patent_app_country] => US [patent_app_date] => 2013-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8434 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14433764 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/433764
Semiconductor device and ceramic circuit substrate, and producing method of semiconductor device Oct 6, 2013 Issued
Array ( [id] => 9220358 [patent_doc_number] => 20140015133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-16 [patent_title] => 'SUPPLY VOLTAGE OR GROUND CONNECTIONS FOR INTEGRATED CIRCUIT DEVICE' [patent_app_type] => utility [patent_app_number] => 14/027515 [patent_app_country] => US [patent_app_date] => 2013-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5523 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14027515 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/027515
Supply voltage or ground connections for integrated circuit device Sep 15, 2013 Issued
Array ( [id] => 11221606 [patent_doc_number] => 09449948 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-20 [patent_title] => 'Chip support substrate, chip support method, three-dimensional integrated circuit, assembly device, and fabrication method of three-dimensional integrated circuit' [patent_app_type] => utility [patent_app_number] => 14/427232 [patent_app_country] => US [patent_app_date] => 2013-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 98 [patent_no_of_words] => 18607 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14427232 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/427232
Chip support substrate, chip support method, three-dimensional integrated circuit, assembly device, and fabrication method of three-dimensional integrated circuit Sep 12, 2013 Issued
Array ( [id] => 10837852 [patent_doc_number] => 08865524 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-21 [patent_title] => 'Lead carrier with print-formed package components' [patent_app_type] => utility [patent_app_number] => 14/017172 [patent_app_country] => US [patent_app_date] => 2013-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 6303 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14017172 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/017172
Lead carrier with print-formed package components Sep 2, 2013 Issued
Array ( [id] => 11259400 [patent_doc_number] => 09484304 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-01 [patent_title] => 'Semiconductor device and method for producing same' [patent_app_type] => utility [patent_app_number] => 14/426117 [patent_app_country] => US [patent_app_date] => 2013-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5059 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14426117 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/426117
Semiconductor device and method for producing same Aug 29, 2013 Issued
Array ( [id] => 9576006 [patent_doc_number] => 08766424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-01 [patent_title] => 'Thin substrate PoP structure' [patent_app_type] => utility [patent_app_number] => 14/013244 [patent_app_country] => US [patent_app_date] => 2013-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3073 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14013244 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/013244
Thin substrate PoP structure Aug 28, 2013 Issued
Array ( [id] => 9552914 [patent_doc_number] => 08759967 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-24 [patent_title] => 'Semiconductor package and package on package having the same' [patent_app_type] => utility [patent_app_number] => 14/013238 [patent_app_country] => US [patent_app_date] => 2013-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7553 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14013238 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/013238
Semiconductor package and package on package having the same Aug 28, 2013 Issued
Menu