Search

Jasmine Jhihan B. Clark

Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )

Most Active Art Unit
2815
Art Unit(s)
2815, 2899, 3621, 2816, 2503
Total Applications
3065
Issued Applications
2831
Pending Applications
98
Abandoned Applications
163

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9729121 [patent_doc_number] => 20140264828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'Method and Apparatus for a Conductive Pillar Structure' [patent_app_type] => utility [patent_app_number] => 13/795081 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3387 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13795081 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/795081
Method and apparatus for a conductive pillar structure Mar 11, 2013 Issued
Array ( [id] => 10583728 [patent_doc_number] => 09305854 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-05 [patent_title] => 'Semiconductor device and method of forming RDL using UV-cured conductive ink over wafer level package' [patent_app_type] => utility [patent_app_number] => 13/795679 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 28 [patent_no_of_words] => 5856 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13795679 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/795679
Semiconductor device and method of forming RDL using UV-cured conductive ink over wafer level package Mar 11, 2013 Issued
Array ( [id] => 9729152 [patent_doc_number] => 20140264860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'RECTIFIER DIODE' [patent_app_type] => utility [patent_app_number] => 13/796489 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4673 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13796489 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/796489
Rectifier diode Mar 11, 2013 Issued
Array ( [id] => 9316601 [patent_doc_number] => 20140048939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-20 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING METAL PLUG AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/796195 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 5672 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13796195 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/796195
Semiconductor device having metal plug and method of manufacturing the same Mar 11, 2013 Issued
Array ( [id] => 9557900 [patent_doc_number] => 20140175612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/795414 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3400 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13795414 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/795414
Semiconductor device and method of manufacturing the same Mar 11, 2013 Issued
Array ( [id] => 9729119 [patent_doc_number] => 20140264827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'METHODS OF FORMING WAFER LEVEL UNDERFILL MATERIALS AND STRUCTURES FORMED THEREBY' [patent_app_type] => utility [patent_app_number] => 13/795021 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4368 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13795021 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/795021
Methods of forming wafer level underfill materials and structures formed thereby Mar 11, 2013 Issued
Array ( [id] => 9360556 [patent_doc_number] => 20140070428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-13 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/795297 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6419 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13795297 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/795297
Semiconductor device and method for manufacturing the same Mar 11, 2013 Issued
Array ( [id] => 9762131 [patent_doc_number] => 08846453 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-09-30 [patent_title] => 'Semiconductor package structure and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 13/794927 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 4268 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13794927 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/794927
Semiconductor package structure and method of manufacturing the same Mar 11, 2013 Issued
Array ( [id] => 9065161 [patent_doc_number] => 20130256917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'SEMICONDUCTOR PACKAGES' [patent_app_type] => utility [patent_app_number] => 13/792942 [patent_app_country] => US [patent_app_date] => 2013-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7271 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13792942 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/792942
Semiconductor packages Mar 10, 2013 Issued
Array ( [id] => 8973842 [patent_doc_number] => 20130207272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-15 [patent_title] => 'AIRGAP-CONTAINING INTERCONNECT STRUCTURE WITH PATTERNABLE LOW-K MATERIAL AND METHOD OF FABRICATING' [patent_app_type] => utility [patent_app_number] => 13/791502 [patent_app_country] => US [patent_app_date] => 2013-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 11513 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13791502 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/791502
Airgap-containing interconnect structure with patternable low-k material and method of fabricating Mar 7, 2013 Issued
Array ( [id] => 9844965 [patent_doc_number] => 08946884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-03 [patent_title] => 'Substrate-less interposer technology for a stacked silicon interconnect technology (SSIT) product' [patent_app_type] => utility [patent_app_number] => 13/791819 [patent_app_country] => US [patent_app_date] => 2013-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4702 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13791819 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/791819
Substrate-less interposer technology for a stacked silicon interconnect technology (SSIT) product Mar 7, 2013 Issued
Array ( [id] => 10611260 [patent_doc_number] => 09331307 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-03 [patent_title] => 'Method for manufacturing organic EL device and organic EL device' [patent_app_type] => utility [patent_app_number] => 14/381478 [patent_app_country] => US [patent_app_date] => 2013-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 29 [patent_no_of_words] => 7780 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14381478 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/381478
Method for manufacturing organic EL device and organic EL device Feb 27, 2013 Issued
Array ( [id] => 10502540 [patent_doc_number] => 09230942 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-05 [patent_title] => 'Semiconductor device including alternating stepped semiconductor die stacks' [patent_app_type] => utility [patent_app_number] => 14/422179 [patent_app_country] => US [patent_app_date] => 2013-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 5664 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14422179 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/422179
Semiconductor device including alternating stepped semiconductor die stacks Feb 25, 2013 Issued
Array ( [id] => 9654268 [patent_doc_number] => 20140225273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-14 [patent_title] => 'CHIP PACKAGE FOR HIGH-COUNT CHIP STACKS' [patent_app_type] => utility [patent_app_number] => 13/764331 [patent_app_country] => US [patent_app_date] => 2013-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6665 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13764331 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/764331
Chip package for high-count chip stacks Feb 10, 2013 Issued
Array ( [id] => 9406260 [patent_doc_number] => 20140097512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-10 [patent_title] => 'HYBRID SEMICONDUCTOR MODULE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/764356 [patent_app_country] => US [patent_app_date] => 2013-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7783 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13764356 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/764356
Hybrid semiconductor module structure Feb 10, 2013 Issued
Array ( [id] => 10042119 [patent_doc_number] => 09082833 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-07-14 [patent_title] => 'Through via recessed reveal structure and method' [patent_app_type] => utility [patent_app_number] => 13/756167 [patent_app_country] => US [patent_app_date] => 2013-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6482 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13756167 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/756167
Through via recessed reveal structure and method Jan 30, 2013 Issued
Array ( [id] => 10329202 [patent_doc_number] => 20150214206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING EMBEDDED CONTROLLER DIE AND METHOD OF MAKING SAME' [patent_app_type] => utility [patent_app_number] => 14/422155 [patent_app_country] => US [patent_app_date] => 2013-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4961 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14422155 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/422155
Semiconductor device including embedded controller die and method of making same Jan 27, 2013 Issued
Array ( [id] => 9455861 [patent_doc_number] => 08716875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-06 [patent_title] => 'Window ball grid array (BGA) semiconductor packages' [patent_app_type] => utility [patent_app_number] => 13/745491 [patent_app_country] => US [patent_app_date] => 2013-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6947 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13745491 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/745491
Window ball grid array (BGA) semiconductor packages Jan 17, 2013 Issued
Array ( [id] => 9876053 [patent_doc_number] => 08963325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'Power device and power device module' [patent_app_type] => utility [patent_app_number] => 13/739372 [patent_app_country] => US [patent_app_date] => 2013-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7465 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13739372 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/739372
Power device and power device module Jan 10, 2013 Issued
Array ( [id] => 9608934 [patent_doc_number] => 08786105 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-07-22 [patent_title] => 'Semiconductor device with chip having low-k-layers' [patent_app_type] => utility [patent_app_number] => 13/739045 [patent_app_country] => US [patent_app_date] => 2013-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4868 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13739045 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/739045
Semiconductor device with chip having low-k-layers Jan 10, 2013 Issued
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