Search

Jasmine Jhihan B. Clark

Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )

Most Active Art Unit
2815
Art Unit(s)
2815, 2899, 3621, 2816, 2503
Total Applications
3065
Issued Applications
2831
Pending Applications
98
Abandoned Applications
163

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10838628 [patent_doc_number] => 08866308 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-21 [patent_title] => 'High density interconnect device and method' [patent_app_type] => utility [patent_app_number] => 13/722128 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2598 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13722128 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/722128
High density interconnect device and method Dec 19, 2012 Issued
Array ( [id] => 9557960 [patent_doc_number] => 20140175671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'STRUCTURE FOR MICROELECTRONIC PACKAGING WITH BOND ELEMENTS TO ENCAPSULATION SURFACE' [patent_app_type] => utility [patent_app_number] => 13/722189 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 16256 [patent_no_of_claims] => 74 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13722189 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/722189
Structure for microelectronic packaging with bond elements to encapsulation surface Dec 19, 2012 Issued
Array ( [id] => 8838976 [patent_doc_number] => 20130134604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-30 [patent_title] => 'METHOD FOR CREATING AND PACKAGING THREE DIMENSIONAL STACKS OF BIOCHIPS CONTAINING MICROELECTRO-MECHANICAL SYSTEMS' [patent_app_type] => utility [patent_app_number] => 13/711118 [patent_app_country] => US [patent_app_date] => 2012-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 6766 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13711118 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/711118
Method for creating and packaging three dimensional stacks of biochips containing microelectro-mechanical systems Dec 10, 2012 Issued
Array ( [id] => 8765059 [patent_doc_number] => 20130093096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-18 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/708207 [patent_app_country] => US [patent_app_date] => 2012-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7192 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13708207 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/708207
Semiconductor device Dec 6, 2012 Issued
Array ( [id] => 8777421 [patent_doc_number] => 20130099396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-25 [patent_title] => 'WAFER BACKSIDE COATING PROCESS WITH PULSED UV LIGHT SOURCE' [patent_app_type] => utility [patent_app_number] => 13/707941 [patent_app_country] => US [patent_app_date] => 2012-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2486 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13707941 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/707941
Wafer backside coating process with pulsed UV light source Dec 6, 2012 Issued
Array ( [id] => 8634854 [patent_doc_number] => 20130026656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-31 [patent_title] => 'SEMICONDUCTOR PACKAGES AND ELECTRONIC SYSTEMS INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/630619 [patent_app_country] => US [patent_app_date] => 2012-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4437 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13630619 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/630619
Semiconductor packages and electronic systems including the same Sep 27, 2012 Issued
Array ( [id] => 9355234 [patent_doc_number] => 08673767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-18 [patent_title] => 'Manufacturing method for semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/624324 [patent_app_country] => US [patent_app_date] => 2012-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 7926 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13624324 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/624324
Manufacturing method for semiconductor device Sep 20, 2012 Issued
Array ( [id] => 11143978 [patent_doc_number] => 09379056 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-28 [patent_title] => 'Semiconductor structure and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/423020 [patent_app_country] => US [patent_app_date] => 2012-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 2302 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14423020 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/423020
Semiconductor structure and method for manufacturing the same Sep 16, 2012 Issued
13/618866 SEMICONDUCTOR DEVICE Sep 13, 2012 Abandoned
Array ( [id] => 8960912 [patent_doc_number] => 20130200514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-08 [patent_title] => 'SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/614125 [patent_app_country] => US [patent_app_date] => 2012-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5605 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13614125 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/614125
Semiconductor packages and methods of manufacturing the same Sep 12, 2012 Issued
Array ( [id] => 8818482 [patent_doc_number] => 20130119527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'SEMICONDUCTOR DIE ASSEMBLIES WITH ENHANCED THERMAL MANAGEMENT, SEMICONDUCTOR DEVICES INCLUDING SAME AND RELATED METHODS' [patent_app_type] => utility [patent_app_number] => 13/613235 [patent_app_country] => US [patent_app_date] => 2012-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6782 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13613235 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/613235
Semiconductor die assemblies with enhanced thermal management and semiconductor devices including same Sep 12, 2012 Issued
Array ( [id] => 10638479 [patent_doc_number] => 09355990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-31 [patent_title] => 'Manufacturing method of device embedded substrate and device embedded substrate manufactured by this method' [patent_app_type] => utility [patent_app_number] => 14/423990 [patent_app_country] => US [patent_app_date] => 2012-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2536 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14423990 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/423990
Manufacturing method of device embedded substrate and device embedded substrate manufactured by this method Sep 10, 2012 Issued
Array ( [id] => 9428263 [patent_doc_number] => 08704343 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-22 [patent_title] => 'Borderless interconnect line structure self-aligned to upper and lower level contact vias' [patent_app_type] => utility [patent_app_number] => 13/607677 [patent_app_country] => US [patent_app_date] => 2012-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7507 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13607677 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/607677
Borderless interconnect line structure self-aligned to upper and lower level contact vias Sep 7, 2012 Issued
Array ( [id] => 9639498 [patent_doc_number] => 20140217608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'SEMICONDUCTOR MODULE, CIRCUIT BOARD' [patent_app_type] => utility [patent_app_number] => 14/239479 [patent_app_country] => US [patent_app_date] => 2012-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 17674 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14239479 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/239479
SEMICONDUCTOR MODULE, CIRCUIT BOARD Sep 5, 2012 Abandoned
Array ( [id] => 8648080 [patent_doc_number] => 20130033810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-07 [patent_title] => 'PRINTED ELECTRONICS' [patent_app_type] => utility [patent_app_number] => 13/603818 [patent_app_country] => US [patent_app_date] => 2012-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 6344 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13603818 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/603818
Printed electronics Sep 4, 2012 Issued
Array ( [id] => 8562961 [patent_doc_number] => 20120325532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'INTERCONNECT STRUCTURE INCLUDING A MODIFIED PHOTORESIST AS A PERMANENT INTERCONNECT DIELECTRIC AND METHOD OF FABRICATING SAME' [patent_app_type] => utility [patent_app_number] => 13/602496 [patent_app_country] => US [patent_app_date] => 2012-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 14639 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13602496 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/602496
Interconnect structure including a modified photoresist as a permanent interconnect dielectric and method of fabricating same Sep 3, 2012 Issued
Array ( [id] => 9971732 [patent_doc_number] => 09018747 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-28 [patent_title] => 'Optical semiconductor apparatus' [patent_app_type] => utility [patent_app_number] => 14/237330 [patent_app_country] => US [patent_app_date] => 2012-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6768 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14237330 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/237330
Optical semiconductor apparatus Aug 16, 2012 Issued
Array ( [id] => 8659597 [patent_doc_number] => 20130040427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-14 [patent_title] => 'FABRICATION METHOD OF PACKAGING SUBSTRATE HAVING THROUGH-HOLED INTERPOSER EMBEDDED THEREIN' [patent_app_type] => utility [patent_app_number] => 13/588030 [patent_app_country] => US [patent_app_date] => 2012-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5445 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13588030 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/588030
Fabrication method of packaging substrate having through-holed interposer embedded therein Aug 16, 2012 Issued
Array ( [id] => 9316598 [patent_doc_number] => 20140048936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-20 [patent_title] => 'HIGH TEMPERATURE INTERCONNECT ASSEMBLIES FOR HIGH TEMPERATURE ELECTRONICS UTILIZING TRANSITION PADS' [patent_app_type] => utility [patent_app_number] => 13/586009 [patent_app_country] => US [patent_app_date] => 2012-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2342 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13586009 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/586009
High temperature interconnect assemblies for high temperature electronics utilizing transition pads Aug 14, 2012 Issued
Array ( [id] => 9065158 [patent_doc_number] => 20130256914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'PACKAGE ON PACKAGE STRUCTURES AND METHODS FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/586629 [patent_app_country] => US [patent_app_date] => 2012-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 5870 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13586629 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/586629
Package on package structures and methods for forming the same Aug 14, 2012 Issued
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