Search

Jasmine Jhihan B. Clark

Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )

Most Active Art Unit
2815
Art Unit(s)
2815, 2899, 3621, 2816, 2503
Total Applications
3065
Issued Applications
2831
Pending Applications
98
Abandoned Applications
163

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9091391 [patent_doc_number] => 20130270702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-17 [patent_title] => 'COPPER INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/586676 [patent_app_country] => US [patent_app_date] => 2012-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2881 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13586676 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/586676
Copper interconnect structure and method for forming the same Aug 14, 2012 Issued
Array ( [id] => 9060493 [patent_doc_number] => 08546932 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-01 [patent_title] => 'Thin substrate PoP structure' [patent_app_type] => utility [patent_app_number] => 13/586375 [patent_app_country] => US [patent_app_date] => 2012-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3035 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13586375 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/586375
Thin substrate PoP structure Aug 14, 2012 Issued
Array ( [id] => 9832422 [patent_doc_number] => 08941241 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-27 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 13/585240 [patent_app_country] => US [patent_app_date] => 2012-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 3263 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13585240 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/585240
Semiconductor device and method of manufacturing the same Aug 13, 2012 Issued
Array ( [id] => 8863338 [patent_doc_number] => 20130147041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'STACK PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/572866 [patent_app_country] => US [patent_app_date] => 2012-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2687 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13572866 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/572866
Stack package structure and fabrication method thereof Aug 12, 2012 Issued
Array ( [id] => 9303925 [patent_doc_number] => 20140042599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-13 [patent_title] => 'MULTI-CHIP MODULE POWER CLIP' [patent_app_type] => utility [patent_app_number] => 13/584015 [patent_app_country] => US [patent_app_date] => 2012-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3340 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13584015 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/584015
Multi-chip module power clip Aug 12, 2012 Issued
Array ( [id] => 9677512 [patent_doc_number] => 08816423 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-26 [patent_title] => 'Semiconducting multi-layer structure and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 13/584366 [patent_app_country] => US [patent_app_date] => 2012-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2351 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13584366 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/584366
Semiconducting multi-layer structure and method for manufacturing the same Aug 12, 2012 Issued
Array ( [id] => 9589239 [patent_doc_number] => 08778779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-15 [patent_title] => 'Semiconductor device and a method for producing semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/571699 [patent_app_country] => US [patent_app_date] => 2012-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 6827 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13571699 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/571699
Semiconductor device and a method for producing semiconductor device Aug 9, 2012 Issued
Array ( [id] => 9663022 [patent_doc_number] => 08810006 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'Interposer system and method' [patent_app_type] => utility [patent_app_number] => 13/572240 [patent_app_country] => US [patent_app_date] => 2012-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8148 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13572240 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/572240
Interposer system and method Aug 9, 2012 Issued
Array ( [id] => 9497254 [patent_doc_number] => 08736076 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-27 [patent_title] => 'Multi-chip stacking of integrated circuit devices using partial device overlap' [patent_app_type] => utility [patent_app_number] => 13/572135 [patent_app_country] => US [patent_app_date] => 2012-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3916 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13572135 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/572135
Multi-chip stacking of integrated circuit devices using partial device overlap Aug 9, 2012 Issued
Array ( [id] => 8657127 [patent_doc_number] => 20130037956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-14 [patent_title] => 'THIN FILM STRUCTURE FOR HIGH DENSITY INDUCTORS AND REDISTRIBUTION IN WAFER LEVEL PACKAGING' [patent_app_type] => utility [patent_app_number] => 13/572376 [patent_app_country] => US [patent_app_date] => 2012-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2264 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13572376 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/572376
Thin film structure for high density inductors and redistribution in wafer level packaging Aug 9, 2012 Issued
Array ( [id] => 9889413 [patent_doc_number] => 08975670 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-10 [patent_title] => 'Semiconductor device and structure for heat removal' [patent_app_type] => utility [patent_app_number] => 13/555152 [patent_app_country] => US [patent_app_date] => 2012-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 62 [patent_figures_cnt] => 74 [patent_no_of_words] => 30737 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13555152 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/555152
Semiconductor device and structure for heat removal Jul 21, 2012 Issued
Array ( [id] => 8486996 [patent_doc_number] => 20120286403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-15 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/554573 [patent_app_country] => US [patent_app_date] => 2012-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3036 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13554573 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/554573
Semiconductor device Jul 19, 2012 Issued
Array ( [id] => 9266706 [patent_doc_number] => 20140021622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-23 [patent_title] => 'OPTIMIZATION METALLIZATION FOR PREVENTION OF DIELECTRIC CRACKING UNDER CONTROLLED COLLAPSE CHIP CONNECTIONS' [patent_app_type] => utility [patent_app_number] => 13/553941 [patent_app_country] => US [patent_app_date] => 2012-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4379 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13553941 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/553941
Optimization metallization for prevention of dielectric cracking under controlled collapse chip connections Jul 19, 2012 Issued
Array ( [id] => 9441542 [patent_doc_number] => 08710656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-29 [patent_title] => 'Redistribution layer (RDL) with variable offset bumps' [patent_app_type] => utility [patent_app_number] => 13/553882 [patent_app_country] => US [patent_app_date] => 2012-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 3379 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13553882 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/553882
Redistribution layer (RDL) with variable offset bumps Jul 19, 2012 Issued
Array ( [id] => 9504260 [patent_doc_number] => 08742578 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-03 [patent_title] => 'Solder volume compensation with C4 process' [patent_app_type] => utility [patent_app_number] => 13/552792 [patent_app_country] => US [patent_app_date] => 2012-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3058 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13552792 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/552792
Solder volume compensation with C4 process Jul 18, 2012 Issued
Array ( [id] => 8777398 [patent_doc_number] => 20130099373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-25 [patent_title] => 'SEMICONDUCTOR PACKAGES INCLUDING A PLURALITY OF UPPER SEMICONDUCTOR DEVICES ON A LOWER SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/550921 [patent_app_country] => US [patent_app_date] => 2012-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 29431 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13550921 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/550921
Semiconductor packages including a plurality of upper semiconductor devices on a lower semiconductor device Jul 16, 2012 Issued
Array ( [id] => 9202457 [patent_doc_number] => 20140001634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-02 [patent_title] => 'CHIP PACKAGE AND METHODS FOR MANUFACTURING A CHIP PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/534144 [patent_app_country] => US [patent_app_date] => 2012-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8833 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13534144 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/534144
Method for manufacturing a chip package Jun 26, 2012 Issued
Array ( [id] => 9832425 [patent_doc_number] => 08941245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-27 [patent_title] => 'Semiconductor package including semiconductor chip with through opening' [patent_app_type] => utility [patent_app_number] => 13/533473 [patent_app_country] => US [patent_app_date] => 2012-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 6303 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13533473 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/533473
Semiconductor package including semiconductor chip with through opening Jun 25, 2012 Issued
Array ( [id] => 8487026 [patent_doc_number] => 20120286433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-15 [patent_title] => 'Robust FEBOL and UBM Structure of C4 Interconnects' [patent_app_type] => utility [patent_app_number] => 13/478076 [patent_app_country] => US [patent_app_date] => 2012-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5112 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13478076 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/478076
Robust FBEOL and UBM structure of C4 interconnects May 21, 2012 Issued
Array ( [id] => 9950968 [patent_doc_number] => 08999754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-07 [patent_title] => 'Integrated circuit package with molded cavity' [patent_app_type] => utility [patent_app_number] => 13/463148 [patent_app_country] => US [patent_app_date] => 2012-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 22 [patent_no_of_words] => 6386 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13463148 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/463148
Integrated circuit package with molded cavity May 2, 2012 Issued
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