
Jasmine Jhihan B. Clark
Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )
| Most Active Art Unit | 2815 |
| Art Unit(s) | 2815, 2899, 3621, 2816, 2503 |
| Total Applications | 3065 |
| Issued Applications | 2831 |
| Pending Applications | 98 |
| Abandoned Applications | 163 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9345605
[patent_doc_number] => 08664755
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-03-04
[patent_title] => 'Power module package and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 13/247603
[patent_app_country] => US
[patent_app_date] => 2011-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 6631
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13247603
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/247603 | Power module package and method for manufacturing the same | Sep 27, 2011 | Issued |
Array
(
[id] => 8730348
[patent_doc_number] => 20130075917
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-03-28
[patent_title] => 'Multi-Chip and Multi-Substrate Reconstitution Based Packaging'
[patent_app_type] => utility
[patent_app_number] => 13/246465
[patent_app_country] => US
[patent_app_date] => 2011-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4522
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13246465
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/246465 | Multi-chip and multi-substrate reconstitution based packaging | Sep 26, 2011 | Issued |
Array
(
[id] => 8166465
[patent_doc_number] => 20120104607
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-03
[patent_title] => 'STACKED SEMICONDUCTOR PACKAGES AND RELATED METHODS'
[patent_app_type] => utility
[patent_app_number] => 13/246408
[patent_app_country] => US
[patent_app_date] => 2011-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4107
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0104/20120104607.pdf
[firstpage_image] =>[orig_patent_app_number] => 13246408
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/246408 | Stacked semiconductor packages and related methods | Sep 26, 2011 | Issued |
Array
(
[id] => 9021048
[patent_doc_number] => 08531034
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-09-10
[patent_title] => 'Semiconductor package and package on package having the same'
[patent_app_type] => utility
[patent_app_number] => 13/244506
[patent_app_country] => US
[patent_app_date] => 2011-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 7527
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13244506
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/244506 | Semiconductor package and package on package having the same | Sep 24, 2011 | Issued |
Array
(
[id] => 9086950
[patent_doc_number] => 08558381
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-10-15
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 13/239800
[patent_app_country] => US
[patent_app_date] => 2011-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 3691
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13239800
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/239800 | Semiconductor device | Sep 21, 2011 | Issued |
Array
(
[id] => 8914078
[patent_doc_number] => 20130175703
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-07-11
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/821782
[patent_app_country] => US
[patent_app_date] => 2011-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6284
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13821782
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/821782 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | Sep 21, 2011 | |
Array
(
[id] => 9227392
[patent_doc_number] => 08633060
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-01-21
[patent_title] => 'Semiconductor device production method and semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 13/238740
[patent_app_country] => US
[patent_app_date] => 2011-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 9246
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13238740
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/238740 | Semiconductor device production method and semiconductor device | Sep 20, 2011 | Issued |
Array
(
[id] => 9010030
[patent_doc_number] => 08525332
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-09-03
[patent_title] => 'Semiconductor device having semiconductor substrate, and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 13/230395
[patent_app_country] => US
[patent_app_date] => 2011-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 43
[patent_no_of_words] => 5500
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13230395
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/230395 | Semiconductor device having semiconductor substrate, and method of manufacturing the same | Sep 11, 2011 | Issued |
Array
(
[id] => 7666905
[patent_doc_number] => 20110316174
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-12-29
[patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/224649
[patent_app_country] => US
[patent_app_date] => 2011-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 6526
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13224649
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/224649 | Semiconductor integrated circuit device | Sep 1, 2011 | Issued |
Array
(
[id] => 8275093
[patent_doc_number] => 20120168959
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-07-05
[patent_title] => 'PACKAGE SUBSTRATE HAVING A THROUGH HOLE AND METHOD OF FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/197177
[patent_app_country] => US
[patent_app_date] => 2011-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2126
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13197177
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/197177 | Package substrate having a through hole and method of fabricating the same | Aug 2, 2011 | Issued |
Array
(
[id] => 8647215
[patent_doc_number] => 20130032944
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-02-07
[patent_title] => 'MICROELECTRONIC PACKAGE WITH STACKED MICROELECTRONIC ELEMENTS AND METHOD FOR MANUFACTURE THEREOF'
[patent_app_type] => utility
[patent_app_number] => 13/195187
[patent_app_country] => US
[patent_app_date] => 2011-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 9547
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13195187
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/195187 | Microelectronic package with stacked microelectronic elements and method for manufacture thereof | Jul 31, 2011 | Issued |
Array
(
[id] => 8910063
[patent_doc_number] => 08482131
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-07-09
[patent_title] => 'Via structure'
[patent_app_type] => utility
[patent_app_number] => 13/194986
[patent_app_country] => US
[patent_app_date] => 2011-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2536
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13194986
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/194986 | Via structure | Jul 30, 2011 | Issued |
Array
(
[id] => 8932573
[patent_doc_number] => 08492272
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-07-23
[patent_title] => 'Passivated through wafer vias in low-doped semiconductor substrates'
[patent_app_type] => utility
[patent_app_number] => 13/193991
[patent_app_country] => US
[patent_app_date] => 2011-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 23
[patent_no_of_words] => 5719
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13193991
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/193991 | Passivated through wafer vias in low-doped semiconductor substrates | Jul 28, 2011 | Issued |
Array
(
[id] => 8180234
[patent_doc_number] => 20120112346
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-10
[patent_title] => 'THIN-FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/193413
[patent_app_country] => US
[patent_app_date] => 2011-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8192
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0112/20120112346.pdf
[firstpage_image] =>[orig_patent_app_number] => 13193413
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/193413 | Thin-film transistor substrate and method of manufacturing the same | Jul 27, 2011 | Issued |
Array
(
[id] => 9483760
[patent_doc_number] => 08729713
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-05-20
[patent_title] => 'Via structure and method thereof'
[patent_app_type] => utility
[patent_app_number] => 13/193313
[patent_app_country] => US
[patent_app_date] => 2011-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 22
[patent_no_of_words] => 7914
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13193313
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/193313 | Via structure and method thereof | Jul 27, 2011 | Issued |
Array
(
[id] => 8634830
[patent_doc_number] => 20130026633
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-01-31
[patent_title] => 'Multilayer Metallization with Stress-Reducing Interlayer'
[patent_app_type] => utility
[patent_app_number] => 13/192376
[patent_app_country] => US
[patent_app_date] => 2011-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2750
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13192376
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/192376 | Multilayer metallization with stress-reducing interlayer | Jul 26, 2011 | Issued |
Array
(
[id] => 9818343
[patent_doc_number] => 08928132
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-01-06
[patent_title] => 'Semiconductor package having through silicon via (TSV) interposer and method of manufacturing the semiconductor package'
[patent_app_type] => utility
[patent_app_number] => 13/188554
[patent_app_country] => US
[patent_app_date] => 2011-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 65
[patent_no_of_words] => 21296
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 24
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13188554
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/188554 | Semiconductor package having through silicon via (TSV) interposer and method of manufacturing the semiconductor package | Jul 21, 2011 | Issued |
Array
(
[id] => 9389941
[patent_doc_number] => 08686545
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-04-01
[patent_title] => 'Semiconductor device and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 13/394430
[patent_app_country] => US
[patent_app_date] => 2011-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 6661
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13394430
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/394430 | Semiconductor device and method for manufacturing the same | Jul 20, 2011 | Issued |
Array
(
[id] => 7571034
[patent_doc_number] => 20110266690
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-11-03
[patent_title] => 'SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, CIRCUIT SUBSTRATE, AND ELECTRONIC APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 13/185039
[patent_app_country] => US
[patent_app_date] => 2011-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7886
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0266/20110266690.pdf
[firstpage_image] =>[orig_patent_app_number] => 13185039
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/185039 | Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus | Jul 17, 2011 | Issued |
Array
(
[id] => 9010004
[patent_doc_number] => 08525305
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-09-03
[patent_title] => 'Lead carrier with print-formed package components'
[patent_app_type] => utility
[patent_app_number] => 13/135210
[patent_app_country] => US
[patent_app_date] => 2011-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 18
[patent_no_of_words] => 6269
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13135210
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/135210 | Lead carrier with print-formed package components | Jun 27, 2011 | Issued |