Search

Jasmine Jhihan B. Clark

Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )

Most Active Art Unit
2815
Art Unit(s)
2815, 2899, 3621, 2816, 2503
Total Applications
3065
Issued Applications
2831
Pending Applications
98
Abandoned Applications
163

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8202990 [patent_doc_number] => 08188579 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-05-29 [patent_title] => 'Semiconductor device including leadframe having power bars and increased I/O' [patent_app_type] => utility [patent_app_number] => 12/965582 [patent_app_country] => US [patent_app_date] => 2010-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 63 [patent_no_of_words] => 23772 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/188/08188579.pdf [firstpage_image] =>[orig_patent_app_number] => 12965582 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/965582
Semiconductor device including leadframe having power bars and increased I/O Dec 9, 2010 Issued
Array ( [id] => 8582987 [patent_doc_number] => 20130001808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'ENCAPSULATION DEVICE HAVING IMPROVED SEALING' [patent_app_type] => utility [patent_app_number] => 13/515447 [patent_app_country] => US [patent_app_date] => 2010-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3962 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13515447 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/515447
Encapsulation device having improved sealing Dec 8, 2010 Issued
Array ( [id] => 6192992 [patent_doc_number] => 20110024746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-03 [patent_title] => 'Semiconductor Device with Test Pads and Pad Connection Unit' [patent_app_type] => utility [patent_app_number] => 12/906266 [patent_app_country] => US [patent_app_date] => 2010-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3414 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20110024746.pdf [firstpage_image] =>[orig_patent_app_number] => 12906266 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/906266
Semiconductor device with test pads and pad connection unit Oct 17, 2010 Issued
Array ( [id] => 8123123 [patent_doc_number] => 20120086112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-12 [patent_title] => 'Multi-Component Electronic System Having Leadframe with Support-Free Cantilever Leads' [patent_app_type] => utility [patent_app_number] => 12/902271 [patent_app_country] => US [patent_app_date] => 2010-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2955 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20120086112.pdf [firstpage_image] =>[orig_patent_app_number] => 12902271 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/902271
Multi-component electronic system having leadframe with support-free with cantilever leads Oct 11, 2010 Issued
Array ( [id] => 8625513 [patent_doc_number] => 08358009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-22 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/901021 [patent_app_country] => US [patent_app_date] => 2010-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 7193 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12901021 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/901021
Semiconductor device Oct 7, 2010 Issued
Array ( [id] => 8123163 [patent_doc_number] => 20120086128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-12 [patent_title] => 'BORDERLESS INTERCONNECT LINE STRUCTURE SELF-ALIGNED TO UPPER AND LOWER LEVEL CONTACT VIAS' [patent_app_type] => utility [patent_app_number] => 12/899911 [patent_app_country] => US [patent_app_date] => 2010-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7454 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20120086128.pdf [firstpage_image] =>[orig_patent_app_number] => 12899911 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/899911
Borderless interconnect line structure self-aligned to upper and lower level contact vias Oct 6, 2010 Issued
Array ( [id] => 6120927 [patent_doc_number] => 20110084400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-14 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 12/923713 [patent_app_country] => US [patent_app_date] => 2010-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10630 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20110084400.pdf [firstpage_image] =>[orig_patent_app_number] => 12923713 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/923713
Semiconductor device and manufacturing method thereof Oct 4, 2010 Issued
Array ( [id] => 8097745 [patent_doc_number] => 20120084478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-05 [patent_title] => 'STACKED DIE WITH VERTICALLY-ALIGNED CONDUCTORS AND METHODS FOR MAKING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/895098 [patent_app_country] => US [patent_app_date] => 2010-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3073 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20120084478.pdf [firstpage_image] =>[orig_patent_app_number] => 12895098 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/895098
Stacked die with vertically-aligned conductors and methods for making the same Sep 29, 2010 Issued
Array ( [id] => 8481001 [patent_doc_number] => 20120280409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-08 [patent_title] => 'Micromechanical Method and Corresponding Assembly for Bonding Semiconductor Substrates and Correspondingly Bonded Semiconductor Chip' [patent_app_type] => utility [patent_app_number] => 13/509163 [patent_app_country] => US [patent_app_date] => 2010-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2239 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13509163 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/509163
Micromechanical method and corresponding assembly for bonding semiconductor substrates and correspondingly bonded semiconductor chip Sep 22, 2010 Issued
Array ( [id] => 9827743 [patent_doc_number] => 08936971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-20 [patent_title] => 'Integrated circuit packaging system with die paddles and method of manufacture thereof' [patent_app_type] => utility [patent_app_number] => 12/884102 [patent_app_country] => US [patent_app_date] => 2010-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4739 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12884102 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/884102
Integrated circuit packaging system with die paddles and method of manufacture thereof Sep 15, 2010 Issued
Array ( [id] => 9504253 [patent_doc_number] => 08742571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-03 [patent_title] => 'Diode array and method for producing a diode array' [patent_app_type] => utility [patent_app_number] => 13/395939 [patent_app_country] => US [patent_app_date] => 2010-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3033 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13395939 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/395939
Diode array and method for producing a diode array Sep 14, 2010 Issued
Array ( [id] => 9245989 [patent_doc_number] => 08610274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-17 [patent_title] => 'Die structure, die arrangement and method of processing a die' [patent_app_type] => utility [patent_app_number] => 12/881257 [patent_app_country] => US [patent_app_date] => 2010-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 8599 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12881257 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/881257
Die structure, die arrangement and method of processing a die Sep 13, 2010 Issued
Array ( [id] => 8538768 [patent_doc_number] => 08314489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-20 [patent_title] => 'Semiconductor module and method for production thereof' [patent_app_type] => utility [patent_app_number] => 12/881003 [patent_app_country] => US [patent_app_date] => 2010-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 35 [patent_no_of_words] => 6477 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12881003 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/881003
Semiconductor module and method for production thereof Sep 12, 2010 Issued
Array ( [id] => 6199810 [patent_doc_number] => 20110062596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'SEMICONDUCTOR CHIP STACKED STRUCTURE AND METHOD OF MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 12/880064 [patent_app_country] => US [patent_app_date] => 2010-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7659 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20110062596.pdf [firstpage_image] =>[orig_patent_app_number] => 12880064 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/880064
SEMICONDUCTOR CHIP STACKED STRUCTURE AND METHOD OF MANUFACTURING SAME Sep 10, 2010 Abandoned
Array ( [id] => 8329184 [patent_doc_number] => 08237279 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-07 [patent_title] => 'Collar structure around solder balls that connect semiconductor die to semiconductor chip package substrate' [patent_app_type] => utility [patent_app_number] => 12/879602 [patent_app_country] => US [patent_app_date] => 2010-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4970 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12879602 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/879602
Collar structure around solder balls that connect semiconductor die to semiconductor chip package substrate Sep 9, 2010 Issued
Array ( [id] => 6177779 [patent_doc_number] => 20110121463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-26 [patent_title] => 'SEMICONDUCTOR PACKAGE, SEMICONDUCTOR DEVICE AND METHODS OF THE SAME' [patent_app_type] => utility [patent_app_number] => 12/880053 [patent_app_country] => US [patent_app_date] => 2010-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7132 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20110121463.pdf [firstpage_image] =>[orig_patent_app_number] => 12880053 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/880053
SEMICONDUCTOR PACKAGE, SEMICONDUCTOR DEVICE AND METHODS OF THE SAME Sep 9, 2010 Abandoned
Array ( [id] => 8436010 [patent_doc_number] => 08283781 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-09 [patent_title] => 'Semiconductor device having pad structure with stress buffer layer' [patent_app_type] => utility [patent_app_number] => 12/879512 [patent_app_country] => US [patent_app_date] => 2010-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 5451 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12879512 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/879512
Semiconductor device having pad structure with stress buffer layer Sep 9, 2010 Issued
Array ( [id] => 7815233 [patent_doc_number] => 20120061853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'SEMICONDUCTOR CHIP DEVICE WITH UNDERFILL' [patent_app_type] => utility [patent_app_number] => 12/878812 [patent_app_country] => US [patent_app_date] => 2010-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5870 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20120061853.pdf [firstpage_image] =>[orig_patent_app_number] => 12878812 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/878812
Semiconductor chip device with underfill Sep 8, 2010 Issued
Array ( [id] => 9524772 [patent_doc_number] => 08749049 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-10 [patent_title] => 'Chip package with a chip embedded in a wiring body' [patent_app_type] => utility [patent_app_number] => 13/497344 [patent_app_country] => US [patent_app_date] => 2010-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4059 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 361 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13497344 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/497344
Chip package with a chip embedded in a wiring body Aug 26, 2010 Issued
Array ( [id] => 6570694 [patent_doc_number] => 20100320531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'STANDING CHIP SCALE PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/852717 [patent_app_country] => US [patent_app_date] => 2010-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 6456 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0320/20100320531.pdf [firstpage_image] =>[orig_patent_app_number] => 12852717 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/852717
Standing chip scale package Aug 8, 2010 Issued
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