
Jasmine Jhihan B. Clark
Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )
| Most Active Art Unit | 2815 |
| Art Unit(s) | 2815, 2899, 3621, 2816, 2503 |
| Total Applications | 3065 |
| Issued Applications | 2831 |
| Pending Applications | 98 |
| Abandoned Applications | 163 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8202990
[patent_doc_number] => 08188579
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-05-29
[patent_title] => 'Semiconductor device including leadframe having power bars and increased I/O'
[patent_app_type] => utility
[patent_app_number] => 12/965582
[patent_app_country] => US
[patent_app_date] => 2010-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 44
[patent_figures_cnt] => 63
[patent_no_of_words] => 23772
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/188/08188579.pdf
[firstpage_image] =>[orig_patent_app_number] => 12965582
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/965582 | Semiconductor device including leadframe having power bars and increased I/O | Dec 9, 2010 | Issued |
Array
(
[id] => 8582987
[patent_doc_number] => 20130001808
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-01-03
[patent_title] => 'ENCAPSULATION DEVICE HAVING IMPROVED SEALING'
[patent_app_type] => utility
[patent_app_number] => 13/515447
[patent_app_country] => US
[patent_app_date] => 2010-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3962
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/515447 | Encapsulation device having improved sealing | Dec 8, 2010 | Issued |
Array
(
[id] => 6192992
[patent_doc_number] => 20110024746
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-02-03
[patent_title] => 'Semiconductor Device with Test Pads and Pad Connection Unit'
[patent_app_type] => utility
[patent_app_number] => 12/906266
[patent_app_country] => US
[patent_app_date] => 2010-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3414
[patent_no_of_claims] => 20
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[pdf_file] => publications/A1/0024/20110024746.pdf
[firstpage_image] =>[orig_patent_app_number] => 12906266
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/906266 | Semiconductor device with test pads and pad connection unit | Oct 17, 2010 | Issued |
Array
(
[id] => 8123123
[patent_doc_number] => 20120086112
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-04-12
[patent_title] => 'Multi-Component Electronic System Having Leadframe with Support-Free Cantilever Leads'
[patent_app_type] => utility
[patent_app_number] => 12/902271
[patent_app_country] => US
[patent_app_date] => 2010-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2955
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/902271 | Multi-component electronic system having leadframe with support-free with cantilever leads | Oct 11, 2010 | Issued |
Array
(
[id] => 8625513
[patent_doc_number] => 08358009
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-01-22
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 12/901021
[patent_app_country] => US
[patent_app_date] => 2010-10-08
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/901021 | Semiconductor device | Oct 7, 2010 | Issued |
Array
(
[id] => 8123163
[patent_doc_number] => 20120086128
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-04-12
[patent_title] => 'BORDERLESS INTERCONNECT LINE STRUCTURE SELF-ALIGNED TO UPPER AND LOWER LEVEL CONTACT VIAS'
[patent_app_type] => utility
[patent_app_number] => 12/899911
[patent_app_country] => US
[patent_app_date] => 2010-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[pdf_file] => publications/A1/0086/20120086128.pdf
[firstpage_image] =>[orig_patent_app_number] => 12899911
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/899911 | Borderless interconnect line structure self-aligned to upper and lower level contact vias | Oct 6, 2010 | Issued |
Array
(
[id] => 6120927
[patent_doc_number] => 20110084400
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[patent_kind] => A1
[patent_issue_date] => 2011-04-14
[patent_title] => 'Semiconductor device and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 12/923713
[patent_app_country] => US
[patent_app_date] => 2010-10-05
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[patent_drawing_sheets_cnt] => 24
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/923713 | Semiconductor device and manufacturing method thereof | Oct 4, 2010 | Issued |
Array
(
[id] => 8097745
[patent_doc_number] => 20120084478
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-04-05
[patent_title] => 'STACKED DIE WITH VERTICALLY-ALIGNED CONDUCTORS AND METHODS FOR MAKING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/895098
[patent_app_country] => US
[patent_app_date] => 2010-09-30
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[patent_drawing_sheets_cnt] => 11
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[patent_no_of_words] => 3073
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/895098 | Stacked die with vertically-aligned conductors and methods for making the same | Sep 29, 2010 | Issued |
Array
(
[id] => 8481001
[patent_doc_number] => 20120280409
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-11-08
[patent_title] => 'Micromechanical Method and Corresponding Assembly for Bonding Semiconductor Substrates and Correspondingly Bonded Semiconductor Chip'
[patent_app_type] => utility
[patent_app_number] => 13/509163
[patent_app_country] => US
[patent_app_date] => 2010-09-23
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[patent_drawing_sheets_cnt] => 4
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/509163 | Micromechanical method and corresponding assembly for bonding semiconductor substrates and correspondingly bonded semiconductor chip | Sep 22, 2010 | Issued |
Array
(
[id] => 9827743
[patent_doc_number] => 08936971
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[patent_kind] => B2
[patent_issue_date] => 2015-01-20
[patent_title] => 'Integrated circuit packaging system with die paddles and method of manufacture thereof'
[patent_app_type] => utility
[patent_app_number] => 12/884102
[patent_app_country] => US
[patent_app_date] => 2010-09-16
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/884102 | Integrated circuit packaging system with die paddles and method of manufacture thereof | Sep 15, 2010 | Issued |
Array
(
[id] => 9504253
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[patent_title] => 'Diode array and method for producing a diode array'
[patent_app_type] => utility
[patent_app_number] => 13/395939
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/395939 | Diode array and method for producing a diode array | Sep 14, 2010 | Issued |
Array
(
[id] => 9245989
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Array
(
[id] => 8538768
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Array
(
[id] => 6199810
[patent_doc_number] => 20110062596
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[patent_title] => 'SEMICONDUCTOR CHIP STACKED STRUCTURE AND METHOD OF MANUFACTURING SAME'
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[patent_app_number] => 12/880064
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Array
(
[id] => 8329184
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[patent_title] => 'Collar structure around solder balls that connect semiconductor die to semiconductor chip package substrate'
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Array
(
[id] => 6177779
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Array
(
[id] => 8436010
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Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/497344 | Chip package with a chip embedded in a wiring body | Aug 26, 2010 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/852717 | Standing chip scale package | Aug 8, 2010 | Issued |