Search

Jasmine Jhihan B. Clark

Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )

Most Active Art Unit
2815
Art Unit(s)
2815, 2899, 3621, 2816, 2503
Total Applications
3065
Issued Applications
2831
Pending Applications
98
Abandoned Applications
163

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6614941 [patent_doc_number] => 20100224999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-09 [patent_title] => 'Method for Producing Metallic Interconnect Lines' [patent_app_type] => utility [patent_app_number] => 12/718587 [patent_app_country] => US [patent_app_date] => 2010-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3695 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20100224999.pdf [firstpage_image] =>[orig_patent_app_number] => 12718587 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/718587
Method for producing metallic interconnect lines Mar 4, 2010 Issued
Array ( [id] => 8933192 [patent_doc_number] => 08492894 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-23 [patent_title] => 'Bump, method for forming the bump, and method for mounting substrate having the bump thereon' [patent_app_type] => utility [patent_app_number] => 13/144411 [patent_app_country] => US [patent_app_date] => 2010-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5653 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13144411 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/144411
Bump, method for forming the bump, and method for mounting substrate having the bump thereon Mar 4, 2010 Issued
Array ( [id] => 8797600 [patent_doc_number] => 08436473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-07 [patent_title] => 'Integrated circuits including air gaps around interconnect structures, and fabrication methods thereof' [patent_app_type] => utility [patent_app_number] => 12/718616 [patent_app_country] => US [patent_app_date] => 2010-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4873 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12718616 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/718616
Integrated circuits including air gaps around interconnect structures, and fabrication methods thereof Mar 4, 2010 Issued
Array ( [id] => 8258113 [patent_doc_number] => 08207613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-26 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/718374 [patent_app_country] => US [patent_app_date] => 2010-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2851 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12718374 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/718374
Semiconductor memory device Mar 4, 2010 Issued
Array ( [id] => 6484921 [patent_doc_number] => 20100258930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'Stacked semiconductor package and method of manufacturing thereof' [patent_app_type] => utility [patent_app_number] => 12/659330 [patent_app_country] => US [patent_app_date] => 2010-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7792 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20100258930.pdf [firstpage_image] =>[orig_patent_app_number] => 12659330 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/659330
Stacked semiconductor package and method of manufacturing thereof Mar 3, 2010 Issued
Array ( [id] => 9153561 [patent_doc_number] => 08586467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-19 [patent_title] => 'Method of mounting electronic component and mounting substrate' [patent_app_type] => utility [patent_app_number] => 13/138582 [patent_app_country] => US [patent_app_date] => 2010-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5682 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13138582 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/138582
Method of mounting electronic component and mounting substrate Feb 24, 2010 Issued
Array ( [id] => 6479285 [patent_doc_number] => 20100213620 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-26 [patent_title] => 'Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package' [patent_app_type] => utility [patent_app_number] => 12/656866 [patent_app_country] => US [patent_app_date] => 2010-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 14446 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20100213620.pdf [firstpage_image] =>[orig_patent_app_number] => 12656866 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/656866
Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package Feb 17, 2010 Issued
Array ( [id] => 7763639 [patent_doc_number] => 08115306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-14 [patent_title] => 'Apparatus and method for packaging circuits' [patent_app_type] => utility [patent_app_number] => 12/705277 [patent_app_country] => US [patent_app_date] => 2010-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 5613 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/115/08115306.pdf [firstpage_image] =>[orig_patent_app_number] => 12705277 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/705277
Apparatus and method for packaging circuits Feb 11, 2010 Issued
Array ( [id] => 7577418 [patent_doc_number] => 20110291300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'DICING SHEET-ATTACHED FILM FOR FORMING SEMICONDUCTOR PROTECTION FILM, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE USING THE SAME, AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/147127 [patent_app_country] => US [patent_app_date] => 2010-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 23775 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20110291300.pdf [firstpage_image] =>[orig_patent_app_number] => 13147127 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/147127
DICING SHEET-ATTACHED FILM FOR FORMING SEMICONDUCTOR PROTECTION FILM, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE USING THE SAME, AND SEMICONDUCTOR DEVICE Feb 9, 2010 Abandoned
Array ( [id] => 7577400 [patent_doc_number] => 20110291282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'JUNCTION BODY, SEMICONDUCTOR MODULE, AND MANUFACTURING METHOD FOR JUNCTION BODY' [patent_app_type] => utility [patent_app_number] => 13/148150 [patent_app_country] => US [patent_app_date] => 2010-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 16106 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 26 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20110291282.pdf [firstpage_image] =>[orig_patent_app_number] => 13148150 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/148150
Junction body, semiconductor module, and manufacturing method for junction body Feb 1, 2010 Issued
Array ( [id] => 8071631 [patent_doc_number] => 20110241209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'Substrate comprising alloy film of metal element having barrier function and metal element having catalytic power' [patent_app_type] => utility [patent_app_number] => 12/998802 [patent_app_country] => US [patent_app_date] => 2010-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5647 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20110241209.pdf [firstpage_image] =>[orig_patent_app_number] => 12998802 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/998802
Substrate comprising alloy film of metal element having barrier function and metal element having catalytic power Jan 27, 2010 Issued
Array ( [id] => 6433245 [patent_doc_number] => 20100187683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-29 [patent_title] => '3-D ICs EQUIPPED WITH DOUBLE SIDED POWER, COOLANT, AND DATA FEATURES' [patent_app_type] => utility [patent_app_number] => 12/694174 [patent_app_country] => US [patent_app_date] => 2010-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5949 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20100187683.pdf [firstpage_image] =>[orig_patent_app_number] => 12694174 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/694174
3-D ICs equipped with double sided power, coolant, and data features Jan 25, 2010 Issued
Array ( [id] => 7586628 [patent_doc_number] => 20110281138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-17 [patent_title] => 'METHOD OF MOUNTING SEMICONDUCTOR CHIPS, SEMICONDUCTOR DEVICE OBTAINED USING THE METHOD,METHOD OF CONNECTING SEMICONDUCTOR CHIPS, THREE-DIMENSIONAL STRUCTURE IN WHICH WIRING IS PROVIDED ON ITS SURFACE, AND METHOD OF PRODUCING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/144112 [patent_app_country] => US [patent_app_date] => 2010-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 22308 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20110281138.pdf [firstpage_image] =>[orig_patent_app_number] => 13144112 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/144112
Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same Jan 25, 2010 Issued
Array ( [id] => 6494896 [patent_doc_number] => 20100200971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'High current capacity inner leads for semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/657428 [patent_app_country] => US [patent_app_date] => 2010-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2065 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20100200971.pdf [firstpage_image] =>[orig_patent_app_number] => 12657428 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/657428
High current capacity inner leads for semiconductor device Jan 20, 2010 Abandoned
Array ( [id] => 4634981 [patent_doc_number] => 08013435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-06 [patent_title] => 'Semiconductor module' [patent_app_type] => utility [patent_app_number] => 12/689746 [patent_app_country] => US [patent_app_date] => 2010-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1762 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/013/08013435.pdf [firstpage_image] =>[orig_patent_app_number] => 12689746 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/689746
Semiconductor module Jan 18, 2010 Issued
Array ( [id] => 7558996 [patent_doc_number] => 20110272827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-10 [patent_title] => 'Adhesive Flexible Barrier Film, Method Of Forming Same, And Organic Electronic Device Including Same' [patent_app_type] => utility [patent_app_number] => 13/144395 [patent_app_country] => US [patent_app_date] => 2010-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7924 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0272/20110272827.pdf [firstpage_image] =>[orig_patent_app_number] => 13144395 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/144395
Adhesive flexible barrier film, method of forming same, and organic electronic device including same Jan 12, 2010 Issued
Array ( [id] => 7752668 [patent_doc_number] => 08110909 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-02-07 [patent_title] => 'Semiconductor package including top-surface terminals for mounting another semiconductor package' [patent_app_type] => utility [patent_app_number] => 12/655724 [patent_app_country] => US [patent_app_date] => 2010-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2370 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/110/08110909.pdf [firstpage_image] =>[orig_patent_app_number] => 12655724 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/655724
Semiconductor package including top-surface terminals for mounting another semiconductor package Jan 4, 2010 Issued
Array ( [id] => 6027120 [patent_doc_number] => 20110079906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-07 [patent_title] => 'PRE-PACKAGED STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/650551 [patent_app_country] => US [patent_app_date] => 2009-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2448 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20110079906.pdf [firstpage_image] =>[orig_patent_app_number] => 12650551 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/650551
PRE-PACKAGED STRUCTURE Dec 30, 2009 Abandoned
Array ( [id] => 9027133 [patent_doc_number] => 08536716 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-09-17 [patent_title] => 'Supply voltage or ground connections for integrated circuit device' [patent_app_type] => utility [patent_app_number] => 12/651122 [patent_app_country] => US [patent_app_date] => 2009-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5482 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12651122 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/651122
Supply voltage or ground connections for integrated circuit device Dec 30, 2009 Issued
Array ( [id] => 8233275 [patent_doc_number] => 08198725 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-12 [patent_title] => 'Heat sink and integrated circuit assembly using the same' [patent_app_type] => utility [patent_app_number] => 12/651006 [patent_app_country] => US [patent_app_date] => 2009-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1539 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/198/08198725.pdf [firstpage_image] =>[orig_patent_app_number] => 12651006 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/651006
Heat sink and integrated circuit assembly using the same Dec 30, 2009 Issued
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