
Jasmine Jhihan B. Clark
Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )
| Most Active Art Unit | 2815 |
| Art Unit(s) | 2815, 2899, 3621, 2816, 2503 |
| Total Applications | 3065 |
| Issued Applications | 2831 |
| Pending Applications | 98 |
| Abandoned Applications | 163 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8329167
[patent_doc_number] => 08237263
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-08-07
[patent_title] => 'Method and apparatus for cooling an integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 12/651002
[patent_app_country] => US
[patent_app_date] => 2009-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 17
[patent_no_of_words] => 6540
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12651002
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/651002 | Method and apparatus for cooling an integrated circuit | Dec 30, 2009 | Issued |
Array
(
[id] => 6153742
[patent_doc_number] => 20110156234
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-06-30
[patent_title] => 'SELF REPAIRING IC PACKAGE DESIGN'
[patent_app_type] => utility
[patent_app_number] => 12/650411
[patent_app_country] => US
[patent_app_date] => 2009-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4775
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0156/20110156234.pdf
[firstpage_image] =>[orig_patent_app_number] => 12650411
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/650411 | Self repairing IC package design | Dec 29, 2009 | Issued |
Array
(
[id] => 6495124
[patent_doc_number] => 20100200994
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-08-12
[patent_title] => 'Semiconductor Device and Method of Manufacturing the Same'
[patent_app_type] => utility
[patent_app_number] => 12/650419
[patent_app_country] => US
[patent_app_date] => 2009-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2983
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0200/20100200994.pdf
[firstpage_image] =>[orig_patent_app_number] => 12650419
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/650419 | Semiconductor device and method of manufacturing the same | Dec 29, 2009 | Issued |
Array
(
[id] => 6115467
[patent_doc_number] => 20110074369
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-03-31
[patent_title] => 'SEMICONDUCTOR APPARATUS AND CALIBRATION METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 12/649193
[patent_app_country] => US
[patent_app_date] => 2009-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3045
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0074/20110074369.pdf
[firstpage_image] =>[orig_patent_app_number] => 12649193
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/649193 | Semiconductor apparatus and calibration method thereof | Dec 28, 2009 | Issued |
Array
(
[id] => 7545930
[patent_doc_number] => 08053904
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-11-08
[patent_title] => 'Semiconductor chip package structure for achieving flip-chip type electrical connection without using wire-bonding process and method for making same'
[patent_app_type] => utility
[patent_app_number] => 12/648646
[patent_app_country] => US
[patent_app_date] => 2009-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 2590
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/053/08053904.pdf
[firstpage_image] =>[orig_patent_app_number] => 12648646
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/648646 | Semiconductor chip package structure for achieving flip-chip type electrical connection without using wire-bonding process and method for making same | Dec 28, 2009 | Issued |
Array
(
[id] => 8147182
[patent_doc_number] => 08164193
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-04-24
[patent_title] => 'Metal wiring of semiconductor device and forming method thereof'
[patent_app_type] => utility
[patent_app_number] => 12/648241
[patent_app_country] => US
[patent_app_date] => 2009-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3786
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/164/08164193.pdf
[firstpage_image] =>[orig_patent_app_number] => 12648241
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/648241 | Metal wiring of semiconductor device and forming method thereof | Dec 27, 2009 | Issued |
Array
(
[id] => 5948491
[patent_doc_number] => 20110031600
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-02-10
[patent_title] => 'SEMICONDUCTOR PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 12/647640
[patent_app_country] => US
[patent_app_date] => 2009-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4346
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0031/20110031600.pdf
[firstpage_image] =>[orig_patent_app_number] => 12647640
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/647640 | Semiconductor package | Dec 27, 2009 | Issued |
Array
(
[id] => 6571366
[patent_doc_number] => 20100320593
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-12-23
[patent_title] => 'Chip Package Structure and Manufacturing Methods Thereof'
[patent_app_type] => utility
[patent_app_number] => 12/648270
[patent_app_country] => US
[patent_app_date] => 2009-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6536
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0320/20100320593.pdf
[firstpage_image] =>[orig_patent_app_number] => 12648270
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/648270 | Chip package structure and manufacturing methods thereof | Dec 27, 2009 | Issued |
Array
(
[id] => 9323451
[patent_doc_number] => 08658471
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-02-25
[patent_title] => 'Structure for multi-row leadframe and semiconductor package thereof and manufacture method thereof'
[patent_app_type] => utility
[patent_app_number] => 13/142172
[patent_app_country] => US
[patent_app_date] => 2009-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 4812
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13142172
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/142172 | Structure for multi-row leadframe and semiconductor package thereof and manufacture method thereof | Dec 22, 2009 | Issued |
Array
(
[id] => 9323451
[patent_doc_number] => 08658471
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-02-25
[patent_title] => 'Structure for multi-row leadframe and semiconductor package thereof and manufacture method thereof'
[patent_app_type] => utility
[patent_app_number] => 13/142172
[patent_app_country] => US
[patent_app_date] => 2009-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 4812
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13142172
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/142172 | Structure for multi-row leadframe and semiconductor package thereof and manufacture method thereof | Dec 22, 2009 | Issued |
Array
(
[id] => 9323451
[patent_doc_number] => 08658471
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-02-25
[patent_title] => 'Structure for multi-row leadframe and semiconductor package thereof and manufacture method thereof'
[patent_app_type] => utility
[patent_app_number] => 13/142172
[patent_app_country] => US
[patent_app_date] => 2009-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 4812
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13142172
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/142172 | Structure for multi-row leadframe and semiconductor package thereof and manufacture method thereof | Dec 22, 2009 | Issued |
Array
(
[id] => 9323451
[patent_doc_number] => 08658471
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-02-25
[patent_title] => 'Structure for multi-row leadframe and semiconductor package thereof and manufacture method thereof'
[patent_app_type] => utility
[patent_app_number] => 13/142172
[patent_app_country] => US
[patent_app_date] => 2009-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 4812
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13142172
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/142172 | Structure for multi-row leadframe and semiconductor package thereof and manufacture method thereof | Dec 22, 2009 | Issued |
Array
(
[id] => 7738941
[patent_doc_number] => 20120018898
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-01-26
[patent_title] => 'VIA STRUCTURE AND METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 13/141609
[patent_app_country] => US
[patent_app_date] => 2009-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 6750
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 22
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0018/20120018898.pdf
[firstpage_image] =>[orig_patent_app_number] => 13141609
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/141609 | Via structure and method thereof | Dec 22, 2009 | Issued |
Array
(
[id] => 8859163
[patent_doc_number] => 08461699
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-06-11
[patent_title] => 'Positive-type photosensitive resin composition, method for producing resist pattern, semiconductor device, and electronic device'
[patent_app_type] => utility
[patent_app_number] => 13/142057
[patent_app_country] => US
[patent_app_date] => 2009-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 17954
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 30
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13142057
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/142057 | Positive-type photosensitive resin composition, method for producing resist pattern, semiconductor device, and electronic device | Dec 15, 2009 | Issued |
Array
(
[id] => 8956580
[patent_doc_number] => 08502359
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-08-06
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 13/141222
[patent_app_country] => US
[patent_app_date] => 2009-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 3046
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13141222
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/141222 | Semiconductor device | Dec 1, 2009 | Issued |
Array
(
[id] => 8738845
[patent_doc_number] => 08410619
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-04-02
[patent_title] => 'Granular epoxy resin composition for encapsulating semiconductor, semiconductor device using the same and method for producing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 13/133800
[patent_app_country] => US
[patent_app_date] => 2009-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 18291
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13133800
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/133800 | Granular epoxy resin composition for encapsulating semiconductor, semiconductor device using the same and method for producing semiconductor device | Dec 1, 2009 | Issued |
Array
(
[id] => 9060520
[patent_doc_number] => 08546959
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-10-01
[patent_title] => 'Resin composition for encapsulating semiconductor, method for producing semiconductor device and semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 13/133752
[patent_app_country] => US
[patent_app_date] => 2009-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 13609
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 268
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13133752
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/133752 | Resin composition for encapsulating semiconductor, method for producing semiconductor device and semiconductor device | Dec 1, 2009 | Issued |
Array
(
[id] => 7577420
[patent_doc_number] => 20110291302
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-12-01
[patent_title] => 'METHOD AND APPARATUS FOR MANUFACTURING AN ELECTRONIC ASSEMBLY, ELECTRONIC ASSEMBLY MANUFACTURED WITH THE METHOD OR IN THE APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 13/139478
[patent_app_country] => US
[patent_app_date] => 2009-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 10562
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 22
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0291/20110291302.pdf
[firstpage_image] =>[orig_patent_app_number] => 13139478
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/139478 | Method and apparatus for manufacturing an electronic assembly, electronic assembly manufactured with the method or in the apparatus | Nov 30, 2009 | Issued |
Array
(
[id] => 9010029
[patent_doc_number] => 08525331
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-09-03
[patent_title] => 'Chip design having integrated fuse and method for the production thereof'
[patent_app_type] => utility
[patent_app_number] => 13/141687
[patent_app_country] => US
[patent_app_date] => 2009-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 3656
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13141687
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/141687 | Chip design having integrated fuse and method for the production thereof | Nov 22, 2009 | Issued |
Array
(
[id] => 4610490
[patent_doc_number] => 07994627
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-08-09
[patent_title] => 'Pad redistribution chip for compactness, method of manufacturing the same, and stacked package using the same'
[patent_app_type] => utility
[patent_app_number] => 12/622614
[patent_app_country] => US
[patent_app_date] => 2009-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 28
[patent_no_of_words] => 4545
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 282
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/994/07994627.pdf
[firstpage_image] =>[orig_patent_app_number] => 12622614
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/622614 | Pad redistribution chip for compactness, method of manufacturing the same, and stacked package using the same | Nov 19, 2009 | Issued |