Search

Jasmine Jhihan B. Clark

Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )

Most Active Art Unit
2815
Art Unit(s)
2815, 2899, 3621, 2816, 2503
Total Applications
3065
Issued Applications
2831
Pending Applications
98
Abandoned Applications
163

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4462431 [patent_doc_number] => 07880295 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-01 [patent_title] => 'Wiring board, semiconductor device in which wiring board is used, and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/618399 [patent_app_country] => US [patent_app_date] => 2009-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 82 [patent_no_of_words] => 30851 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/880/07880295.pdf [firstpage_image] =>[orig_patent_app_number] => 12618399 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/618399
Wiring board, semiconductor device in which wiring board is used, and method for manufacturing the same Nov 12, 2009 Issued
Array ( [id] => 7480145 [patent_doc_number] => 20110248397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-13 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING STACKED COMPONENTS' [patent_app_type] => utility [patent_app_number] => 13/130169 [patent_app_country] => US [patent_app_date] => 2009-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2115 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20110248397.pdf [firstpage_image] =>[orig_patent_app_number] => 13130169 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/130169
Semiconductor device having stacked components Nov 9, 2009 Issued
Array ( [id] => 9233397 [patent_doc_number] => 08598705 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-03 [patent_title] => 'Composite substrate for a semiconductor chip' [patent_app_type] => utility [patent_app_number] => 13/128960 [patent_app_country] => US [patent_app_date] => 2009-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3996 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13128960 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/128960
Composite substrate for a semiconductor chip Nov 8, 2009 Issued
Array ( [id] => 8154880 [patent_doc_number] => 20120098110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'Supporting Body for a Semiconductor Component, Semiconductor Element and Method for Production of a Supporting Body' [patent_app_type] => utility [patent_app_number] => 13/126761 [patent_app_country] => US [patent_app_date] => 2009-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8732 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20120098110.pdf [firstpage_image] =>[orig_patent_app_number] => 13126761 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/126761
Carrier body for a semiconductor component, semiconductor component and method for producing a carrier body Oct 21, 2009 Issued
Array ( [id] => 7496864 [patent_doc_number] => 20110260304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'LEADFRAME FOR ELECTRONIC COMPONENTS' [patent_app_type] => utility [patent_app_number] => 13/124115 [patent_app_country] => US [patent_app_date] => 2009-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1919 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20110260304.pdf [firstpage_image] =>[orig_patent_app_number] => 13124115 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/124115
Leadframe for electronic components Oct 11, 2009 Issued
Array ( [id] => 6027145 [patent_doc_number] => 20110079916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-07 [patent_title] => 'ELECTRONIC ASSEMBLIES INCLUDING MECHANICALLY SECURED PROTRUDING BONDING CONDUCTOR JOINTS' [patent_app_type] => utility [patent_app_number] => 12/572615 [patent_app_country] => US [patent_app_date] => 2009-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6045 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20110079916.pdf [firstpage_image] =>[orig_patent_app_number] => 12572615 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/572615
Electronic assemblies including mechanically secured protruding bonding conductor joints Oct 1, 2009 Issued
Array ( [id] => 8690576 [patent_doc_number] => 08390105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-05 [patent_title] => 'Lead frame substrate, manufacturing method thereof, and semiconductor apparatus' [patent_app_type] => utility [patent_app_number] => 12/998098 [patent_app_country] => US [patent_app_date] => 2009-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4265 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12998098 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/998098
Lead frame substrate, manufacturing method thereof, and semiconductor apparatus Sep 27, 2009 Issued
Array ( [id] => 9483743 [patent_doc_number] => 08729695 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-20 [patent_title] => 'Wafer level package and a method of forming a wafer level package' [patent_app_type] => utility [patent_app_number] => 13/497611 [patent_app_country] => US [patent_app_date] => 2009-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 40 [patent_no_of_words] => 13314 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13497611 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/497611
Wafer level package and a method of forming a wafer level package Sep 24, 2009 Issued
Array ( [id] => 5972692 [patent_doc_number] => 20110068446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-24 [patent_title] => 'Semiconductor Chip Attach Configuration Having Improved Thermal Characteristics' [patent_app_type] => utility [patent_app_number] => 12/562385 [patent_app_country] => US [patent_app_date] => 2009-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4254 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20110068446.pdf [firstpage_image] =>[orig_patent_app_number] => 12562385 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/562385
Semiconductor chip attach configuration having improved thermal characteristics Sep 17, 2009 Issued
Array ( [id] => 6286261 [patent_doc_number] => 20100237490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/561627 [patent_app_country] => US [patent_app_date] => 2009-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2884 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20100237490.pdf [firstpage_image] =>[orig_patent_app_number] => 12561627 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/561627
PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF Sep 16, 2009 Abandoned
Array ( [id] => 6199778 [patent_doc_number] => 20110062564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'SEMICONDUCTOR DIE CONTAINING LATERAL EDGE SHAPES AND TEXTURES' [patent_app_type] => utility [patent_app_number] => 12/561988 [patent_app_country] => US [patent_app_date] => 2009-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6096 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20110062564.pdf [firstpage_image] =>[orig_patent_app_number] => 12561988 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/561988
Semiconductor die containing lateral edge shapes and textures Sep 16, 2009 Issued
Array ( [id] => 6201029 [patent_doc_number] => 20110063815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'Robust FBEOL and UBM Structure of C4 Interconnects' [patent_app_type] => utility [patent_app_number] => 12/560769 [patent_app_country] => US [patent_app_date] => 2009-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5112 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20110063815.pdf [firstpage_image] =>[orig_patent_app_number] => 12560769 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/560769
Robust FBEOL and UBM structure of C4 interconnects Sep 15, 2009 Issued
Array ( [id] => 7796347 [patent_doc_number] => 08125055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-28 [patent_title] => 'Packaging technology' [patent_app_type] => utility [patent_app_number] => 12/557945 [patent_app_country] => US [patent_app_date] => 2009-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 4652 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/125/08125055.pdf [firstpage_image] =>[orig_patent_app_number] => 12557945 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/557945
Packaging technology Sep 10, 2009 Issued
Array ( [id] => 6358924 [patent_doc_number] => 20100078800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'LOW COST FLEXIBLE SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 12/557896 [patent_app_country] => US [patent_app_date] => 2009-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4068 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20100078800.pdf [firstpage_image] =>[orig_patent_app_number] => 12557896 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/557896
Low cost flexible substrate Sep 10, 2009 Issued
Array ( [id] => 6342656 [patent_doc_number] => 20100084758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-08 [patent_title] => 'Semiconductor package' [patent_app_type] => utility [patent_app_number] => 12/585274 [patent_app_country] => US [patent_app_date] => 2009-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5983 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20100084758.pdf [firstpage_image] =>[orig_patent_app_number] => 12585274 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/585274
Semiconductor package Sep 9, 2009 Abandoned
Array ( [id] => 6004126 [patent_doc_number] => 20110057296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-10 [patent_title] => 'DELAMINATION RESISTANT PACKAGED DIE HAVING SUPPORT AND SHAPED DIE HAVING PROTRUDING LIP ON SUPPORT' [patent_app_type] => utility [patent_app_number] => 12/555646 [patent_app_country] => US [patent_app_date] => 2009-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4536 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20110057296.pdf [firstpage_image] =>[orig_patent_app_number] => 12555646 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/555646
Delamination resistant packaged die having support and shaped die having protruding lip on support Sep 7, 2009 Issued
Array ( [id] => 9627159 [patent_doc_number] => 08796844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-05 [patent_title] => 'Package structure' [patent_app_type] => utility [patent_app_number] => 13/393746 [patent_app_country] => US [patent_app_date] => 2009-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 4525 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13393746 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/393746
Package structure Sep 1, 2009 Issued
Array ( [id] => 9576020 [patent_doc_number] => 08766438 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-01 [patent_title] => 'Package structure' [patent_app_type] => utility [patent_app_number] => 13/393459 [patent_app_country] => US [patent_app_date] => 2009-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4982 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13393459 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/393459
Package structure Aug 31, 2009 Issued
Array ( [id] => 8538776 [patent_doc_number] => 08314496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-20 [patent_title] => 'Semiconductor device and inductor' [patent_app_type] => utility [patent_app_number] => 12/550646 [patent_app_country] => US [patent_app_date] => 2009-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3282 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12550646 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/550646
Semiconductor device and inductor Aug 30, 2009 Issued
Array ( [id] => 5371677 [patent_doc_number] => 20090309237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-17 [patent_title] => 'SEMICONDUCTOR PACKAGE SYSTEM WITH SUBSTRATE HAVING DIFFERENT BONDABLE HEIGHTS AT LEAD FINGER TIPS' [patent_app_type] => utility [patent_app_number] => 12/547439 [patent_app_country] => US [patent_app_date] => 2009-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6466 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0309/20090309237.pdf [firstpage_image] =>[orig_patent_app_number] => 12547439 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/547439
Semiconductor package system with substrate having different bondable heights at lead finger tips Aug 24, 2009 Issued
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