
Jasmine Jhihan B. Clark
Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )
| Most Active Art Unit | 2815 |
| Art Unit(s) | 2815, 2899, 3621, 2816, 2503 |
| Total Applications | 3065 |
| Issued Applications | 2831 |
| Pending Applications | 98 |
| Abandoned Applications | 163 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 55093
[patent_doc_number] => 07768138
[patent_country] => US
[patent_kind] => B2
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[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
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[patent_app_country] => US
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[pdf_file] => patents/07/768/07768138.pdf
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Array
(
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[patent_doc_number] => 20090008758
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[patent_kind] => A1
[patent_issue_date] => 2009-01-08
[patent_title] => 'USE OF DISCRETE CONDUCTIVE LAYER IN SEMICONDUCTOR DEVICE TO RE-ROUTE BONDING WIRES FOR SEMICONDUCTOR DEVICE PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 12/209106
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Array
(
[id] => 45186
[patent_doc_number] => 07777326
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[patent_issue_date] => 2010-08-17
[patent_title] => 'Routing structure of re-distribution layer and method for re-distributing routing structure in integrated circuit'
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[patent_app_number] => 12/207676
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[patent_app_date] => 2008-09-10
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Array
(
[id] => 7492431
[patent_doc_number] => 08030770
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[patent_kind] => B1
[patent_issue_date] => 2011-10-04
[patent_title] => 'Substrateless package'
[patent_app_type] => utility
[patent_app_number] => 12/207206
[patent_app_country] => US
[patent_app_date] => 2008-09-09
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Array
(
[id] => 4513831
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[patent_title] => 'Getter formed by laser-treatment and methods of making same'
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Array
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[patent_title] => 'Semiconductor device having a suspended isolating interconnect'
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Array
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[patent_title] => 'INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING AN OFFSET STACKED CONFIGURATION'
[patent_app_type] => utility
[patent_app_number] => 12/201896
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/201896 | Integrated circuit package system employing an offset stacked configuration | Aug 28, 2008 | Issued |
Array
(
[id] => 4849697
[patent_doc_number] => 20080315439
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[patent_kind] => A1
[patent_issue_date] => 2008-12-25
[patent_title] => 'QUAD FLAT NON-LEADED CHIP PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 12/201236
[patent_app_country] => US
[patent_app_date] => 2008-08-29
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/201236 | Quad flat non-leaded chip package | Aug 28, 2008 | Issued |
Array
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[id] => 5449883
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[patent_issue_date] => 2009-03-12
[patent_title] => 'SEMICONDUCTOR PACKAGE HAVING RESIN SUBSTRATE WITH RECESS AND METHOD OF FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/202036
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/202036 | Semiconductor package having resin substrate with recess and method of fabricating the same | Aug 28, 2008 | Issued |
Array
(
[id] => 4538248
[patent_doc_number] => 07888781
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[patent_title] => 'Micro-layered lead frame semiconductor packages'
[patent_app_type] => utility
[patent_app_number] => 12/199065
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/199065 | Micro-layered lead frame semiconductor packages | Aug 26, 2008 | Issued |
Array
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[id] => 4756691
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[patent_title] => 'CHIP PACKAGE'
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Array
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Array
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Array
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Array
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Array
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