Search

Jasmine Jhihan B. Clark

Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )

Most Active Art Unit
2815
Art Unit(s)
2815, 2899, 3621, 2816, 2503
Total Applications
3065
Issued Applications
2831
Pending Applications
98
Abandoned Applications
163

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 55093 [patent_doc_number] => 07768138 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-03 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/212186 [patent_app_country] => US [patent_app_date] => 2008-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 28 [patent_no_of_words] => 9933 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/768/07768138.pdf [firstpage_image] =>[orig_patent_app_number] => 12212186 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/212186
Semiconductor device Sep 16, 2008 Issued
Array ( [id] => 5293832 [patent_doc_number] => 20090008758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'USE OF DISCRETE CONDUCTIVE LAYER IN SEMICONDUCTOR DEVICE TO RE-ROUTE BONDING WIRES FOR SEMICONDUCTOR DEVICE PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/209106 [patent_app_country] => US [patent_app_date] => 2008-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5007 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20090008758.pdf [firstpage_image] =>[orig_patent_app_number] => 12209106 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/209106
Use of discrete conductive layer in semiconductor device to re-route bonding wires for semiconductor device package Sep 10, 2008 Issued
Array ( [id] => 45186 [patent_doc_number] => 07777326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-17 [patent_title] => 'Routing structure of re-distribution layer and method for re-distributing routing structure in integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/207676 [patent_app_country] => US [patent_app_date] => 2008-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2654 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/777/07777326.pdf [firstpage_image] =>[orig_patent_app_number] => 12207676 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/207676
Routing structure of re-distribution layer and method for re-distributing routing structure in integrated circuit Sep 9, 2008 Issued
Array ( [id] => 7492431 [patent_doc_number] => 08030770 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-10-04 [patent_title] => 'Substrateless package' [patent_app_type] => utility [patent_app_number] => 12/207206 [patent_app_country] => US [patent_app_date] => 2008-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 3841 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/030/08030770.pdf [firstpage_image] =>[orig_patent_app_number] => 12207206 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/207206
Substrateless package Sep 8, 2008 Issued
Array ( [id] => 4513831 [patent_doc_number] => 07910391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-22 [patent_title] => 'Getter formed by laser-treatment and methods of making same' [patent_app_type] => utility [patent_app_number] => 12/204296 [patent_app_country] => US [patent_app_date] => 2008-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3522 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/910/07910391.pdf [firstpage_image] =>[orig_patent_app_number] => 12204296 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/204296
Getter formed by laser-treatment and methods of making same Sep 3, 2008 Issued
Array ( [id] => 4487723 [patent_doc_number] => 07902665 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-08 [patent_title] => 'Semiconductor device having a suspended isolating interconnect' [patent_app_type] => utility [patent_app_number] => 12/202835 [patent_app_country] => US [patent_app_date] => 2008-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4522 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/902/07902665.pdf [firstpage_image] =>[orig_patent_app_number] => 12202835 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/202835
Semiconductor device having a suspended isolating interconnect Sep 1, 2008 Issued
Array ( [id] => 5319874 [patent_doc_number] => 20090057864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING AN OFFSET STACKED CONFIGURATION' [patent_app_type] => utility [patent_app_number] => 12/201896 [patent_app_country] => US [patent_app_date] => 2008-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11003 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20090057864.pdf [firstpage_image] =>[orig_patent_app_number] => 12201896 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/201896
Integrated circuit package system employing an offset stacked configuration Aug 28, 2008 Issued
Array ( [id] => 4849697 [patent_doc_number] => 20080315439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'QUAD FLAT NON-LEADED CHIP PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/201236 [patent_app_country] => US [patent_app_date] => 2008-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4171 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20080315439.pdf [firstpage_image] =>[orig_patent_app_number] => 12201236 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/201236
Quad flat non-leaded chip package Aug 28, 2008 Issued
Array ( [id] => 5449883 [patent_doc_number] => 20090065919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'SEMICONDUCTOR PACKAGE HAVING RESIN SUBSTRATE WITH RECESS AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/202036 [patent_app_country] => US [patent_app_date] => 2008-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4393 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20090065919.pdf [firstpage_image] =>[orig_patent_app_number] => 12202036 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/202036
Semiconductor package having resin substrate with recess and method of fabricating the same Aug 28, 2008 Issued
Array ( [id] => 4538248 [patent_doc_number] => 07888781 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-15 [patent_title] => 'Micro-layered lead frame semiconductor packages' [patent_app_type] => utility [patent_app_number] => 12/199065 [patent_app_country] => US [patent_app_date] => 2008-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 2832 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/888/07888781.pdf [firstpage_image] =>[orig_patent_app_number] => 12199065 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/199065
Micro-layered lead frame semiconductor packages Aug 26, 2008 Issued
Array ( [id] => 4756691 [patent_doc_number] => 20080308916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'CHIP PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/198536 [patent_app_country] => US [patent_app_date] => 2008-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3594 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0308/20080308916.pdf [firstpage_image] =>[orig_patent_app_number] => 12198536 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/198536
Chip package Aug 25, 2008 Issued
Array ( [id] => 4578882 [patent_doc_number] => 07825513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Electrode structure in semiconductor device and related technology' [patent_app_type] => utility [patent_app_number] => 12/197615 [patent_app_country] => US [patent_app_date] => 2008-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 5427 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/825/07825513.pdf [firstpage_image] =>[orig_patent_app_number] => 12197615 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/197615
Electrode structure in semiconductor device and related technology Aug 24, 2008 Issued
Array ( [id] => 5334558 [patent_doc_number] => 20090051022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-26 [patent_title] => 'LEAD FRAME STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/196506 [patent_app_country] => US [patent_app_date] => 2008-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2320 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20090051022.pdf [firstpage_image] =>[orig_patent_app_number] => 12196506 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/196506
LEAD FRAME STRUCTURE Aug 21, 2008 Abandoned
Array ( [id] => 4849695 [patent_doc_number] => 20080315437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'Tape wiring substrate and chip-on-film package using the same' [patent_app_type] => utility [patent_app_number] => 12/222986 [patent_app_country] => US [patent_app_date] => 2008-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3329 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20080315437.pdf [firstpage_image] =>[orig_patent_app_number] => 12222986 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/222986
Tape wiring substrate and chip-on-film package using the same Aug 20, 2008 Issued
Array ( [id] => 6447996 [patent_doc_number] => 20100038758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-18 [patent_title] => 'SEMICONDUCTOR MODULE WITH TWO COOLING SURFACES AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/192496 [patent_app_country] => US [patent_app_date] => 2008-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4018 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20100038758.pdf [firstpage_image] =>[orig_patent_app_number] => 12192496 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/192496
Semiconductor module with two cooling surfaces and method Aug 14, 2008 Issued
Array ( [id] => 4575559 [patent_doc_number] => 07859118 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-28 [patent_title] => 'Multi-substrate region-based package and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 12/228755 [patent_app_country] => US [patent_app_date] => 2008-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3944 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/859/07859118.pdf [firstpage_image] =>[orig_patent_app_number] => 12228755 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/228755
Multi-substrate region-based package and method for fabricating the same Aug 14, 2008 Issued
Array ( [id] => 34736 [patent_doc_number] => 07786585 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-31 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 12/188591 [patent_app_country] => US [patent_app_date] => 2008-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 40 [patent_no_of_words] => 17248 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 376 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/786/07786585.pdf [firstpage_image] =>[orig_patent_app_number] => 12188591 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/188591
Semiconductor integrated circuit device Aug 7, 2008 Issued
Array ( [id] => 4527010 [patent_doc_number] => 07952191 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-31 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/187636 [patent_app_country] => US [patent_app_date] => 2008-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 7069 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/952/07952191.pdf [firstpage_image] =>[orig_patent_app_number] => 12187636 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/187636
Semiconductor device Aug 6, 2008 Issued
Array ( [id] => 4457686 [patent_doc_number] => 07893526 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-22 [patent_title] => 'Semiconductor package apparatus' [patent_app_type] => utility [patent_app_number] => 12/220996 [patent_app_country] => US [patent_app_date] => 2008-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2434 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/893/07893526.pdf [firstpage_image] =>[orig_patent_app_number] => 12220996 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/220996
Semiconductor package apparatus Jul 29, 2008 Issued
Array ( [id] => 7527910 [patent_doc_number] => 08044506 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-25 [patent_title] => 'Thermal-emitting memory module, thermal-emitting module socket, and computer system' [patent_app_type] => utility [patent_app_number] => 12/181488 [patent_app_country] => US [patent_app_date] => 2008-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5726 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/044/08044506.pdf [firstpage_image] =>[orig_patent_app_number] => 12181488 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/181488
Thermal-emitting memory module, thermal-emitting module socket, and computer system Jul 28, 2008 Issued
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