Jasmine Jhihan B. Clark

Array ( [id] => 5469888 [patent_doc_number] => 20090243054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'I/O CONNECTION SCHEME FOR QFN LEADFRAME AND PACKAGE STRUCTURES' [patent_app_type] => utility [patent_app_number] => 12/059526 [patent_app_country] => US [patent_app_date] => 2008-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6958 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20090243054.pdf [firstpage_image] =>[orig_patent_app_number] => 12059526 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5469911 [patent_doc_number] => 20090243077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'INTEGRATED CIRCUIT PACKAGE SYSTEM WITH RIGID LOCKING LEAD' [patent_app_type] => utility [patent_app_number] => 12/055642 [patent_app_country] => US [patent_app_date] => 2008-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5621 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20090243077.pdf [firstpage_image] =>[orig_patent_app_number] => 12055642 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5469886 [patent_doc_number] => 20090243052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'Electronic device with shielding structure and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/076982 [patent_app_country] => US [patent_app_date] => 2008-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4618 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20090243052.pdf [firstpage_image] =>[orig_patent_app_number] => 12076982 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5469901 [patent_doc_number] => 20090243067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 12/054701 [patent_app_country] => US [patent_app_date] => 2008-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4928 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20090243067.pdf [firstpage_image] =>[orig_patent_app_number] => 12054701 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4715325 [patent_doc_number] => 20080237847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'Power semiconductor module, and power semiconductor device having the module mounted therein' [patent_app_type] => utility [patent_app_number] => 12/079012 [patent_app_country] => US [patent_app_date] => 2008-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9143 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20080237847.pdf [firstpage_image] =>[orig_patent_app_number] => 12079012 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4489101 [patent_doc_number] => 07884455 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/051221 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 59 [patent_no_of_words] => 11076 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/884/07884455.pdf [firstpage_image] =>[orig_patent_app_number] => 12051221 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4479786 [patent_doc_number] => 07906857 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-03-15 [patent_title] => 'Molded integrated circuit package and method of forming a molded integrated circuit package' [patent_app_type] => utility [patent_app_number] => 12/047676 [patent_app_country] => US [patent_app_date] => 2008-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 36 [patent_no_of_words] => 4197 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/906/07906857.pdf [firstpage_image] =>[orig_patent_app_number] => 12047676 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 24944 [patent_doc_number] => 07795701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-14 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 12/046001 [patent_app_country] => US [patent_app_date] => 2008-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4720 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/795/07795701.pdf [firstpage_image] =>[orig_patent_app_number] => 12046001 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4947035 [patent_doc_number] => 20080303161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-11 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/042716 [patent_app_country] => US [patent_app_date] => 2008-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6362 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0303/20080303161.pdf [firstpage_image] =>[orig_patent_app_number] => 12042716 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4673439 [patent_doc_number] => 20080211067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/040952 [patent_app_country] => US [patent_app_date] => 2008-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2973 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20080211067.pdf [firstpage_image] =>[orig_patent_app_number] => 12040952 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6304454 [patent_doc_number] => 20100109154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-06 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/529925 [patent_app_country] => US [patent_app_date] => 2008-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4017 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20100109154.pdf [firstpage_image] =>[orig_patent_app_number] => 12529925 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4863901 [patent_doc_number] => 20080142960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'CIRCUIT DEVICE WITH AT LEAST PARTIAL PACKAGING AND METHOD FOR FORMING' [patent_app_type] => utility [patent_app_number] => 12/039434 [patent_app_country] => US [patent_app_date] => 2008-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4164 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20080142960.pdf [firstpage_image] =>[orig_patent_app_number] => 12039434 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 34757 [patent_doc_number] => 07786596 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-31 [patent_title] => 'Hermetic seal and reliable bonding structures for 3D applications' [patent_app_type] => utility [patent_app_number] => 12/038501 [patent_app_country] => US [patent_app_date] => 2008-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 4128 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/786/07786596.pdf [firstpage_image] =>[orig_patent_app_number] => 12038501 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4578982 [patent_doc_number] => 07825525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Layout and process to contact sub-lithographic structures' [patent_app_type] => utility [patent_app_number] => 12/034901 [patent_app_country] => US [patent_app_date] => 2008-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 4486 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/825/07825525.pdf [firstpage_image] =>[orig_patent_app_number] => 12034901 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4726978 [patent_doc_number] => 20080206519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'Component assembly' [patent_app_type] => utility [patent_app_number] => 12/069786 [patent_app_country] => US [patent_app_date] => 2008-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1506 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20080206519.pdf [firstpage_image] =>[orig_patent_app_number] => 12069786 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4446016 [patent_doc_number] => 07863724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-04 [patent_title] => 'Circuit substrate having post-fed die side power supply connections' [patent_app_type] => utility [patent_app_number] => 12/029574 [patent_app_country] => US [patent_app_date] => 2008-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3067 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/863/07863724.pdf [firstpage_image] =>[orig_patent_app_number] => 12029574 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6342649 [patent_doc_number] => 20100084756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-08 [patent_title] => 'DUAL OR MULTIPLE ROW PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/525265 [patent_app_country] => US [patent_app_date] => 2008-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7598 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20100084756.pdf [firstpage_image] =>[orig_patent_app_number] => 12525265 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4863899 [patent_doc_number] => 20080142958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'HERMETIC SEAL AND RELIABLE BONDING STRUCTURES FOR 3D APPLICATIONS' [patent_app_type] => utility [patent_app_number] => 12/026776 [patent_app_country] => US [patent_app_date] => 2008-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4108 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20080142958.pdf [firstpage_image] =>[orig_patent_app_number] => 12026776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4587039 [patent_doc_number] => 07851907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-14 [patent_title] => 'Semiconductor integrated circuit package having electrically disconnected solder balls for mounting' [patent_app_type] => utility [patent_app_number] => 12/022211 [patent_app_country] => US [patent_app_date] => 2008-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 5736 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/851/07851907.pdf [firstpage_image] =>[orig_patent_app_number] => 12022211 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5307579 [patent_doc_number] => 20090014860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'Multi-chip stack structure and fabricating method thereof' [patent_app_type] => utility [patent_app_number] => 12/011832 [patent_app_country] => US [patent_app_date] => 2008-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3304 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20090014860.pdf [firstpage_image] =>[orig_patent_app_number] => 12011832 [rel_patent_id] =>[rel_patent_doc_number] =>)