Search

Jasmine Jhihan B. Clark

Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )

Most Active Art Unit
2815
Art Unit(s)
2815, 2899, 3621, 2816, 2503
Total Applications
3065
Issued Applications
2831
Pending Applications
98
Abandoned Applications
163

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6369179 [patent_doc_number] => 20100314752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-16 [patent_title] => 'FORMING AN ETCHED PLANARISED PHOTONIC CRYSTAL STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/744199 [patent_app_country] => US [patent_app_date] => 2007-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2986 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0314/20100314752.pdf [firstpage_image] =>[orig_patent_app_number] => 12744199 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/744199
FORMING AN ETCHED PLANARISED PHOTONIC CRYSTAL STRUCTURE Nov 21, 2007 Abandoned
Array ( [id] => 143238 [patent_doc_number] => 07692311 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-06 [patent_title] => 'POP (package-on-package) device encapsulating soldered joints between external leads' [patent_app_type] => utility [patent_app_number] => 11/984772 [patent_app_country] => US [patent_app_date] => 2007-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2773 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/692/07692311.pdf [firstpage_image] =>[orig_patent_app_number] => 11984772 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/984772
POP (package-on-package) device encapsulating soldered joints between external leads Nov 20, 2007 Issued
Array ( [id] => 5275554 [patent_doc_number] => 20090127686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-21 [patent_title] => 'Stacking die package structure for semiconductor devices and method of the same' [patent_app_type] => utility [patent_app_number] => 11/984781 [patent_app_country] => US [patent_app_date] => 2007-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4021 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20090127686.pdf [firstpage_image] =>[orig_patent_app_number] => 11984781 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/984781
Stacking die package structure for semiconductor devices and method of the same Nov 20, 2007 Abandoned
Array ( [id] => 4896933 [patent_doc_number] => 20080116546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-22 [patent_title] => 'Lead frame unit, semiconductor package having a lead frame unit, stacked semiconductor package having a semiconductor package and methods of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/984762 [patent_app_country] => US [patent_app_date] => 2007-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9499 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20080116546.pdf [firstpage_image] =>[orig_patent_app_number] => 11984762 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/984762
Lead frame unit, semiconductor package having a lead frame unit, stacked semiconductor package having a semiconductor package and methods of manufacturing the same Nov 20, 2007 Issued
Array ( [id] => 4820793 [patent_doc_number] => 20080122064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/943142 [patent_app_country] => US [patent_app_date] => 2007-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6332 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20080122064.pdf [firstpage_image] =>[orig_patent_app_number] => 11943142 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/943142
Semiconductor device Nov 19, 2007 Issued
Array ( [id] => 367012 [patent_doc_number] => 07479697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-20 [patent_title] => 'Resilient carrier assembly for an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/940304 [patent_app_country] => US [patent_app_date] => 2007-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 3324 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/479/07479697.pdf [firstpage_image] =>[orig_patent_app_number] => 11940304 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/940304
Resilient carrier assembly for an integrated circuit Nov 13, 2007 Issued
Array ( [id] => 4715306 [patent_doc_number] => 20080237828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'SEMICONDUCTOR DEVICE PACKAGE WITH DIE RECEIVING THROUGH-HOLE AND DUAL BUILD-UP LAYERS OVER BOTH SIDE-SURFACES FOR WLP AND METHOD OF THE SAME' [patent_app_type] => utility [patent_app_number] => 11/936596 [patent_app_country] => US [patent_app_date] => 2007-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5464 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20080237828.pdf [firstpage_image] =>[orig_patent_app_number] => 11936596 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/936596
SEMICONDUCTOR DEVICE PACKAGE WITH DIE RECEIVING THROUGH-HOLE AND DUAL BUILD-UP LAYERS OVER BOTH SIDE-SURFACES FOR WLP AND METHOD OF THE SAME Nov 6, 2007 Abandoned
Array ( [id] => 4768767 [patent_doc_number] => 20080054423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'APPARATUS AND METHOD FOR PACKAGING CIRCUITS' [patent_app_type] => utility [patent_app_number] => 11/934556 [patent_app_country] => US [patent_app_date] => 2007-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5679 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20080054423.pdf [firstpage_image] =>[orig_patent_app_number] => 11934556 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/934556
Apparatus and method for packaging circuits Nov 1, 2007 Issued
Array ( [id] => 6495173 [patent_doc_number] => 20100201000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'BOND PAD SUPPORT STRUCTURE FOR SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/678405 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3211 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20100201000.pdf [firstpage_image] =>[orig_patent_app_number] => 12678405 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/678405
Bond pad support structure for semiconductor device Oct 30, 2007 Issued
Array ( [id] => 253057 [patent_doc_number] => 07579692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-25 [patent_title] => 'Method for forming a bump, semiconductor device and method of fabricating same, semiconductor chip, circuit board, and electronic instrument' [patent_app_type] => utility [patent_app_number] => 11/980126 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 9311 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/579/07579692.pdf [firstpage_image] =>[orig_patent_app_number] => 11980126 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/980126
Method for forming a bump, semiconductor device and method of fabricating same, semiconductor chip, circuit board, and electronic instrument Oct 29, 2007 Issued
Array ( [id] => 7530835 [patent_doc_number] => 07843058 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-30 [patent_title] => 'Flip chip packages with spacers separating heat sinks and substrates' [patent_app_type] => utility [patent_app_number] => 11/928971 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2676 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/843/07843058.pdf [firstpage_image] =>[orig_patent_app_number] => 11928971 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/928971
Flip chip packages with spacers separating heat sinks and substrates Oct 29, 2007 Issued
Array ( [id] => 196639 [patent_doc_number] => 07635917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-22 [patent_title] => 'Three-dimensional package and method of making the same' [patent_app_type] => utility [patent_app_number] => 11/928041 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2901 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/635/07635917.pdf [firstpage_image] =>[orig_patent_app_number] => 11928041 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/928041
Three-dimensional package and method of making the same Oct 29, 2007 Issued
Array ( [id] => 4743416 [patent_doc_number] => 20080088017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/907552 [patent_app_country] => US [patent_app_date] => 2007-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2393 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20080088017.pdf [firstpage_image] =>[orig_patent_app_number] => 11907552 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/907552
Semiconductor integrated circuit device Oct 14, 2007 Abandoned
Array ( [id] => 4685681 [patent_doc_number] => 20080029862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING DIE STACKING' [patent_app_type] => utility [patent_app_number] => 11/869738 [patent_app_country] => US [patent_app_date] => 2007-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3811 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20080029862.pdf [firstpage_image] =>[orig_patent_app_number] => 11869738 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/869738
Integrated circuit package system including die stacking Oct 8, 2007 Issued
Array ( [id] => 5425911 [patent_doc_number] => 20090085221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'Multi-host interface controller with USB PHY/analog functions integrated in a single package' [patent_app_type] => utility [patent_app_number] => 11/906582 [patent_app_country] => US [patent_app_date] => 2007-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1412 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20090085221.pdf [firstpage_image] =>[orig_patent_app_number] => 11906582 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/906582
Multi-host interface controller with USB PHY/analog functions integrated in a single package Oct 1, 2007 Issued
Array ( [id] => 132808 [patent_doc_number] => 07701044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-20 [patent_title] => 'Chip package for image sensor and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/906481 [patent_app_country] => US [patent_app_date] => 2007-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4336 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/701/07701044.pdf [firstpage_image] =>[orig_patent_app_number] => 11906481 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/906481
Chip package for image sensor and method of manufacturing the same Oct 1, 2007 Issued
Array ( [id] => 4465941 [patent_doc_number] => 07936074 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-03 [patent_title] => 'Programmable system in package' [patent_app_type] => utility [patent_app_number] => 11/861204 [patent_app_country] => US [patent_app_date] => 2007-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5514 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/936/07936074.pdf [firstpage_image] =>[orig_patent_app_number] => 11861204 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/861204
Programmable system in package Sep 24, 2007 Issued
Array ( [id] => 72745 [patent_doc_number] => 07755180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-13 [patent_title] => 'Integrated circuit package-in-package system' [patent_app_type] => utility [patent_app_number] => 11/858861 [patent_app_country] => US [patent_app_date] => 2007-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 5659 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/755/07755180.pdf [firstpage_image] =>[orig_patent_app_number] => 11858861 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/858861
Integrated circuit package-in-package system Sep 19, 2007 Issued
Array ( [id] => 8760010 [patent_doc_number] => 08420530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Nano-interconnects for atomic and molecular scale circuits' [patent_app_type] => utility [patent_app_number] => 12/672885 [patent_app_country] => US [patent_app_date] => 2007-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 2940 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12672885 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/672885
Nano-interconnects for atomic and molecular scale circuits Aug 9, 2007 Issued
Array ( [id] => 4685701 [patent_doc_number] => 20080029882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'Thermal Interconnect System and Method of Production Thereof' [patent_app_type] => utility [patent_app_number] => 11/834852 [patent_app_country] => US [patent_app_date] => 2007-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4684 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20080029882.pdf [firstpage_image] =>[orig_patent_app_number] => 11834852 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/834852
Thermal Interconnect System and Method of Production Thereof Aug 6, 2007 Abandoned
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