Search

Jasmine Jhihan B. Clark

Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )

Most Active Art Unit
2815
Art Unit(s)
2815, 2899, 3621, 2816, 2503
Total Applications
3065
Issued Applications
2831
Pending Applications
98
Abandoned Applications
163

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18008649 [patent_doc_number] => 20220367416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => SEMICONDUCTOR PACKAGE HAVING PACKAGE SUBSTRATE [patent_app_type] => utility [patent_app_number] => 17/671065 [patent_app_country] => US [patent_app_date] => 2022-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16193 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17671065 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/671065
Semiconductor package having package substrate Feb 13, 2022 Issued
Array ( [id] => 19720376 [patent_doc_number] => 12205920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Enhanced thermal control of a hybrid chip assembly [patent_app_type] => utility [patent_app_number] => 17/592037 [patent_app_country] => US [patent_app_date] => 2022-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 10119 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17592037 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/592037
Enhanced thermal control of a hybrid chip assembly Feb 2, 2022 Issued
Array ( [id] => 17615463 [patent_doc_number] => 20220157743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => PACKAGE STRUCTURE WITH STACKED SEMICONDUCTOR DIES [patent_app_type] => utility [patent_app_number] => 17/587290 [patent_app_country] => US [patent_app_date] => 2022-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6719 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17587290 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/587290
Package structure with stacked semiconductor dies Jan 27, 2022 Issued
Array ( [id] => 19414854 [patent_doc_number] => 12080691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/585122 [patent_app_country] => US [patent_app_date] => 2022-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 7682 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17585122 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/585122
Semiconductor devices Jan 25, 2022 Issued
Array ( [id] => 17599476 [patent_doc_number] => 20220149050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/584592 [patent_app_country] => US [patent_app_date] => 2022-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17584592 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/584592
Semiconductor device and method for fabricating the same Jan 25, 2022 Issued
Array ( [id] => 19399766 [patent_doc_number] => 12074154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Package structure [patent_app_type] => utility [patent_app_number] => 17/584308 [patent_app_country] => US [patent_app_date] => 2022-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 31 [patent_no_of_words] => 7075 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17584308 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/584308
Package structure Jan 24, 2022 Issued
Array ( [id] => 17993432 [patent_doc_number] => 20220359469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => SEMICONDUCTOR PACKAGE, AND A PACKAGE ON PACKAGE TYPE SEMICONDUCTOR PACKAGE HAVING THE SAME [patent_app_type] => utility [patent_app_number] => 17/578621 [patent_app_country] => US [patent_app_date] => 2022-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12188 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17578621 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/578621
Semiconductor package, and a package on package type semiconductor package having the same Jan 18, 2022 Issued
Array ( [id] => 17833696 [patent_doc_number] => 20220271000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/648200 [patent_app_country] => US [patent_app_date] => 2022-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6086 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648200 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/648200
Semiconductor structure and manufacturing method thereof Jan 17, 2022 Issued
Array ( [id] => 19582601 [patent_doc_number] => 12148729 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => Semiconductor package structure having interposer substrate, and stacked semiconductor package structure including the same [patent_app_type] => utility [patent_app_number] => 17/577653 [patent_app_country] => US [patent_app_date] => 2022-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 32 [patent_no_of_words] => 13559 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17577653 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/577653
Semiconductor package structure having interposer substrate, and stacked semiconductor package structure including the same Jan 17, 2022 Issued
Array ( [id] => 17833699 [patent_doc_number] => 20220271003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => THREE-DIMENSIONAL STACKED FAN-OUT PACKAGING STRUCTURE AND METHOD MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 17/574106 [patent_app_country] => US [patent_app_date] => 2022-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6799 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17574106 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/574106
Three-dimensional stacked fan-out packaging structure and method making the same Jan 11, 2022 Issued
Array ( [id] => 17764788 [patent_doc_number] => 20220238401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => Seamless Interconnect Thresholds using Dielectric Fluid Channels [patent_app_type] => utility [patent_app_number] => 17/573874 [patent_app_country] => US [patent_app_date] => 2022-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2752 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17573874 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/573874
Seamless interconnect thresholds using dielectric fluid channels Jan 11, 2022 Issued
Array ( [id] => 17833714 [patent_doc_number] => 20220271018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => DOUBLE-LAYER STACKED 3D FAN-OUT PACKAGING STRUCTURE AND METHOD MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 17/564121 [patent_app_country] => US [patent_app_date] => 2021-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6646 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564121 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/564121
Double-layer stacked 3D fan-out packaging structure and method making the same Dec 27, 2021 Issued
Array ( [id] => 17833705 [patent_doc_number] => 20220271009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => DOUBLE-LAYER PACKAGED 3D FAN-OUT PACKAGING STRUCTURE AND METHOD MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 17/564124 [patent_app_country] => US [patent_app_date] => 2021-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6709 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564124 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/564124
DOUBLE-LAYER PACKAGED 3D FAN-OUT PACKAGING STRUCTURE AND METHOD MAKING THE SAME Dec 27, 2021 Pending
Array ( [id] => 20126154 [patent_doc_number] => 20250241185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => DISPLAY PANEL, MANUFACTURING METHOD THEREOF, AND MOBILE TERMINAL [patent_app_type] => utility [patent_app_number] => 17/637538 [patent_app_country] => US [patent_app_date] => 2021-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2504 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17637538 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/637538
DISPLAY PANEL, MANUFACTURING METHOD THEREOF, AND MOBILE TERMINAL Dec 27, 2021 Pending
Array ( [id] => 18473146 [patent_doc_number] => 20230207434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => CHIP-MIDDLE TYPE FAN-OUT PANEL-LEVEL PACKAGE AND PACKAGING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/562211 [patent_app_country] => US [patent_app_date] => 2021-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3548 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17562211 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/562211
Chip-middle type fan-out panel-level package and packaging method thereof Dec 26, 2021 Issued
Array ( [id] => 19873765 [patent_doc_number] => 12266636 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Stacked die package including a multi-contact interconnect [patent_app_type] => utility [patent_app_number] => 17/556547 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13905 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17556547 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/556547
Stacked die package including a multi-contact interconnect Dec 19, 2021 Issued
Array ( [id] => 18456343 [patent_doc_number] => 20230197625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => SEMICONDUCTOR DEVICE WITH INTEGRATED DECOUPLING AND ALIGNMENT FEATURES [patent_app_type] => utility [patent_app_number] => 17/556149 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8620 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17556149 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/556149
Semiconductor device with integrated decoupling and alignment features Dec 19, 2021 Issued
Array ( [id] => 17523128 [patent_doc_number] => 20220108977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-07 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/644452 [patent_app_country] => US [patent_app_date] => 2021-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23786 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17644452 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/644452
Semiconductor device Dec 14, 2021 Issued
Array ( [id] => 19781522 [patent_doc_number] => 12230560 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Semiconductor package structure [patent_app_type] => utility [patent_app_number] => 17/546191 [patent_app_country] => US [patent_app_date] => 2021-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 10663 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17546191 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/546191
Semiconductor package structure Dec 8, 2021 Issued
Array ( [id] => 19213715 [patent_doc_number] => 12002787 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-04 [patent_title] => Multi-die package structure and multi-die co-packing method [patent_app_type] => utility [patent_app_number] => 17/545229 [patent_app_country] => US [patent_app_date] => 2021-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3165 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17545229 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/545229
Multi-die package structure and multi-die co-packing method Dec 7, 2021 Issued
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