Search

Jasmine Jhihan B. Clark

Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )

Most Active Art Unit
2815
Art Unit(s)
2815, 2899, 3621, 2816, 2503
Total Applications
3065
Issued Applications
2831
Pending Applications
98
Abandoned Applications
163

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4890795 [patent_doc_number] => 20080099892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'Stacked chip packaging with heat sink structure' [patent_app_type] => utility [patent_app_number] => 11/882551 [patent_app_country] => US [patent_app_date] => 2007-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7931 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20080099892.pdf [firstpage_image] =>[orig_patent_app_number] => 11882551 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/882551
Stacked chip packaging with heat sink structure Aug 1, 2007 Issued
Array ( [id] => 5359421 [patent_doc_number] => 20090034215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'Method and Apparatus for Providing Electrically Isolated Closely Spaced Features on a Printed Circuit Board' [patent_app_type] => utility [patent_app_number] => 11/830348 [patent_app_country] => US [patent_app_date] => 2007-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2844 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20090034215.pdf [firstpage_image] =>[orig_patent_app_number] => 11830348 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/830348
Method and apparatus for providing electrically isolated closely spaced features on a printed circuit board Jul 29, 2007 Issued
Array ( [id] => 178305 [patent_doc_number] => 07656014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-02 [patent_title] => 'Semiconductor device and method for manufacturing same' [patent_app_type] => utility [patent_app_number] => 11/779801 [patent_app_country] => US [patent_app_date] => 2007-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 7658 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/656/07656014.pdf [firstpage_image] =>[orig_patent_app_number] => 11779801 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/779801
Semiconductor device and method for manufacturing same Jul 17, 2007 Issued
Array ( [id] => 112815 [patent_doc_number] => 07719096 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-18 [patent_title] => 'Semiconductor device and method for manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/827041 [patent_app_country] => US [patent_app_date] => 2007-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2972 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/719/07719096.pdf [firstpage_image] =>[orig_patent_app_number] => 11827041 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/827041
Semiconductor device and method for manufacturing a semiconductor device Jul 8, 2007 Issued
Array ( [id] => 113879 [patent_doc_number] => 07714426 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-05-11 [patent_title] => 'Ball grid array package format layers and structure' [patent_app_type] => utility [patent_app_number] => 11/825643 [patent_app_country] => US [patent_app_date] => 2007-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 3033 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/714/07714426.pdf [firstpage_image] =>[orig_patent_app_number] => 11825643 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/825643
Ball grid array package format layers and structure Jul 6, 2007 Issued
Array ( [id] => 43583 [patent_doc_number] => 07781828 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Integrated semiconductor chip with lateral thermal insulation' [patent_app_type] => utility [patent_app_number] => 11/774051 [patent_app_country] => US [patent_app_date] => 2007-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4358 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/781/07781828.pdf [firstpage_image] =>[orig_patent_app_number] => 11774051 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/774051
Integrated semiconductor chip with lateral thermal insulation Jul 5, 2007 Issued
Array ( [id] => 5008168 [patent_doc_number] => 20070278645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'STACKED PACKAGE ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 11/769536 [patent_app_country] => US [patent_app_date] => 2007-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3592 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20070278645.pdf [firstpage_image] =>[orig_patent_app_number] => 11769536 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/769536
Stacked package electronic device Jun 26, 2007 Issued
Array ( [id] => 4849472 [patent_doc_number] => 20080315214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'Solderless Integrated Package Connector and Heat Sink for LED' [patent_app_type] => utility [patent_app_number] => 11/765291 [patent_app_country] => US [patent_app_date] => 2007-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3434 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20080315214.pdf [firstpage_image] =>[orig_patent_app_number] => 11765291 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/765291
Solderless integrated package connector and heat sink for LED Jun 18, 2007 Issued
11/812224 LEADLESS LEADFRAME WITH AN IMPROVED DIE PAD FOR MOLD LOCKING Jun 14, 2007 Abandoned
Array ( [id] => 632 [patent_doc_number] => RE041826 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2010-10-19 [patent_title] => 'Semiconductor device' [patent_app_type] => reissue [patent_app_number] => 11/808572 [patent_app_country] => US [patent_app_date] => 2007-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 10332 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/041/RE041826.pdf [firstpage_image] =>[orig_patent_app_number] => 11808572 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/808572
Semiconductor device Jun 10, 2007 Issued
Array ( [id] => 4946913 [patent_doc_number] => 20080303039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-11 [patent_title] => 'Mount for a Semiconductor Light Emitting Device' [patent_app_type] => utility [patent_app_number] => 11/760521 [patent_app_country] => US [patent_app_date] => 2007-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5432 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0303/20080303039.pdf [firstpage_image] =>[orig_patent_app_number] => 11760521 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/760521
Mount for a semiconductor light emitting device Jun 7, 2007 Issued
Array ( [id] => 33701 [patent_doc_number] => 07791185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-07 [patent_title] => 'Pin grid array package substrate including pins having curved pin heads' [patent_app_type] => utility [patent_app_number] => 11/758401 [patent_app_country] => US [patent_app_date] => 2007-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2904 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/791/07791185.pdf [firstpage_image] =>[orig_patent_app_number] => 11758401 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/758401
Pin grid array package substrate including pins having curved pin heads Jun 4, 2007 Issued
Array ( [id] => 383402 [patent_doc_number] => 07307354 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-11 [patent_title] => 'Integrated circuit (IC) carrier assembly incorporating an integrated circuit (IC) retainer' [patent_app_type] => utility [patent_app_number] => 11/758644 [patent_app_country] => US [patent_app_date] => 2007-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 3295 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/307/07307354.pdf [firstpage_image] =>[orig_patent_app_number] => 11758644 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/758644
Integrated circuit (IC) carrier assembly incorporating an integrated circuit (IC) retainer Jun 4, 2007 Issued
Array ( [id] => 303944 [patent_doc_number] => 07535084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-19 [patent_title] => 'Multi-chip package with a single die pad' [patent_app_type] => utility [patent_app_number] => 11/749441 [patent_app_country] => US [patent_app_date] => 2007-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1634 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/535/07535084.pdf [firstpage_image] =>[orig_patent_app_number] => 11749441 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/749441
Multi-chip package with a single die pad May 15, 2007 Issued
Array ( [id] => 5026293 [patent_doc_number] => 20070267739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-22 [patent_title] => 'Power Semiconductor Module' [patent_app_type] => utility [patent_app_number] => 11/749211 [patent_app_country] => US [patent_app_date] => 2007-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5092 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20070267739.pdf [firstpage_image] =>[orig_patent_app_number] => 11749211 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/749211
Power semiconductor module May 15, 2007 Issued
Array ( [id] => 4856554 [patent_doc_number] => 20080265404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'Structure and Methods of Processing for Solder Thermal Interface Materials for Chip Cooling' [patent_app_type] => utility [patent_app_number] => 11/742161 [patent_app_country] => US [patent_app_date] => 2007-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2183 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20080265404.pdf [firstpage_image] =>[orig_patent_app_number] => 11742161 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/742161
Structure and methods of processing for solder thermal interface materials for chip cooling Apr 29, 2007 Issued
Array ( [id] => 8846836 [patent_doc_number] => 08456023 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-04 [patent_title] => 'Semiconductor wafer processing' [patent_app_type] => utility [patent_app_number] => 12/596267 [patent_app_country] => US [patent_app_date] => 2007-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1532 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12596267 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/596267
Semiconductor wafer processing Apr 26, 2007 Issued
Array ( [id] => 4890767 [patent_doc_number] => 20080099864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'CHIP PACKAGE, METHOD OF MAKING SAME AND DIGITAL CAMERA MODULE USING THE PACKAGE' [patent_app_type] => utility [patent_app_number] => 11/695441 [patent_app_country] => US [patent_app_date] => 2007-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4342 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20080099864.pdf [firstpage_image] =>[orig_patent_app_number] => 11695441 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/695441
Chip package, method of making same and digital camera module using the package Apr 1, 2007 Issued
Array ( [id] => 4503750 [patent_doc_number] => 07919859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-05 [patent_title] => 'Copper die bumps with electromigration cap and plated solder' [patent_app_type] => utility [patent_app_number] => 11/728082 [patent_app_country] => US [patent_app_date] => 2007-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2467 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/919/07919859.pdf [firstpage_image] =>[orig_patent_app_number] => 11728082 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/728082
Copper die bumps with electromigration cap and plated solder Mar 22, 2007 Issued
Array ( [id] => 196638 [patent_doc_number] => 07635916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-22 [patent_title] => 'Integrated circuit package with top-side conduction cooling' [patent_app_type] => utility [patent_app_number] => 11/690502 [patent_app_country] => US [patent_app_date] => 2007-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2830 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/635/07635916.pdf [firstpage_image] =>[orig_patent_app_number] => 11690502 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/690502
Integrated circuit package with top-side conduction cooling Mar 22, 2007 Issued
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