Search

Jasmine Jhihan B. Clark

Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )

Most Active Art Unit
2815
Art Unit(s)
2815, 2899, 3621, 2816, 2503
Total Applications
3065
Issued Applications
2831
Pending Applications
98
Abandoned Applications
163

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5054429 [patent_doc_number] => 20070057350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Semiconductor component and method of assembling the same' [patent_app_type] => utility [patent_app_number] => 11/224301 [patent_app_country] => US [patent_app_date] => 2005-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5741 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20070057350.pdf [firstpage_image] =>[orig_patent_app_number] => 11224301 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/224301
Semiconductor component and method of assembling the same Sep 12, 2005 Issued
Array ( [id] => 5741322 [patent_doc_number] => 20060087045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-27 [patent_title] => 'Substrate having a built-in chip and external connection terminals on both sides and a method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/224821 [patent_app_country] => US [patent_app_date] => 2005-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6204 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20060087045.pdf [firstpage_image] =>[orig_patent_app_number] => 11224821 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/224821
Substrate having a built-in chip and external connection terminals on both sides and a method for manufacturing the same Sep 12, 2005 Issued
Array ( [id] => 4876720 [patent_doc_number] => 20080150103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'Multi-Die Ic Package and Manufacturing Method' [patent_app_type] => utility [patent_app_number] => 11/662431 [patent_app_country] => US [patent_app_date] => 2005-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 1957 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20080150103.pdf [firstpage_image] =>[orig_patent_app_number] => 11662431 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/662431
Multi-die IC package and manufacturing method Sep 8, 2005 Issued
Array ( [id] => 418715 [patent_doc_number] => 07276387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-02 [patent_title] => 'Castellation wafer level packaging of integrated circuit chips' [patent_app_type] => utility [patent_app_number] => 11/221521 [patent_app_country] => US [patent_app_date] => 2005-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 44 [patent_no_of_words] => 8697 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/276/07276387.pdf [firstpage_image] =>[orig_patent_app_number] => 11221521 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/221521
Castellation wafer level packaging of integrated circuit chips Sep 6, 2005 Issued
Array ( [id] => 5738555 [patent_doc_number] => 20060008946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-12 [patent_title] => 'Castellation wafer level packaging of integrated circuit chips' [patent_app_type] => utility [patent_app_number] => 11/222462 [patent_app_country] => US [patent_app_date] => 2005-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8689 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20060008946.pdf [firstpage_image] =>[orig_patent_app_number] => 11222462 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/222462
Castellation wafer level packaging of integrated circuit chips Sep 6, 2005 Issued
Array ( [id] => 370190 [patent_doc_number] => 07476965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-13 [patent_title] => 'Electronic device with integrated heat distributor' [patent_app_type] => utility [patent_app_number] => 11/575751 [patent_app_country] => US [patent_app_date] => 2005-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 2946 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/476/07476965.pdf [firstpage_image] =>[orig_patent_app_number] => 11575751 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/575751
Electronic device with integrated heat distributor Sep 6, 2005 Issued
Array ( [id] => 5180728 [patent_doc_number] => 20070052070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-08 [patent_title] => 'Die pad for semiconductor packages and methods of making and using same' [patent_app_type] => utility [patent_app_number] => 11/220761 [patent_app_country] => US [patent_app_date] => 2005-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7620 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20070052070.pdf [firstpage_image] =>[orig_patent_app_number] => 11220761 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/220761
Die pad for semiconductor packages and methods of making and using same Sep 5, 2005 Issued
Array ( [id] => 5708176 [patent_doc_number] => 20060049520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-09 [patent_title] => 'Semiconductor device mounting structure for reducing thermal stress and warpage' [patent_app_type] => utility [patent_app_number] => 11/217292 [patent_app_country] => US [patent_app_date] => 2005-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4183 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20060049520.pdf [firstpage_image] =>[orig_patent_app_number] => 11217292 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/217292
Semiconductor device mounting structure for reducing thermal stress and warpage Sep 1, 2005 Issued
Array ( [id] => 5145791 [patent_doc_number] => 20070045845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Ball grid array interface structure and method' [patent_app_type] => utility [patent_app_number] => 11/216961 [patent_app_country] => US [patent_app_date] => 2005-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1614 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20070045845.pdf [firstpage_image] =>[orig_patent_app_number] => 11216961 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/216961
Ball grid array interface structure and method Aug 30, 2005 Abandoned
Array ( [id] => 428994 [patent_doc_number] => 07268430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-11 [patent_title] => 'Semiconductor device and process for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/213882 [patent_app_country] => US [patent_app_date] => 2005-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5749 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/268/07268430.pdf [firstpage_image] =>[orig_patent_app_number] => 11213882 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/213882
Semiconductor device and process for manufacturing the same Aug 29, 2005 Issued
Array ( [id] => 513340 [patent_doc_number] => 07196414 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-27 [patent_title] => 'Semiconductor package with heat sink' [patent_app_type] => utility [patent_app_number] => 11/212182 [patent_app_country] => US [patent_app_date] => 2005-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3625 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/196/07196414.pdf [firstpage_image] =>[orig_patent_app_number] => 11212182 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/212182
Semiconductor package with heat sink Aug 25, 2005 Issued
Array ( [id] => 4992288 [patent_doc_number] => 20070007632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'Optical package with double formed leadframe' [patent_app_type] => utility [patent_app_number] => 11/207752 [patent_app_country] => US [patent_app_date] => 2005-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3504 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20070007632.pdf [firstpage_image] =>[orig_patent_app_number] => 11207752 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/207752
Optical package with double formed leadframe Aug 21, 2005 Issued
Array ( [id] => 840793 [patent_doc_number] => 07391107 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-24 [patent_title] => 'Signal routing on redistribution layer' [patent_app_type] => utility [patent_app_number] => 11/206481 [patent_app_country] => US [patent_app_date] => 2005-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2700 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/391/07391107.pdf [firstpage_image] =>[orig_patent_app_number] => 11206481 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/206481
Signal routing on redistribution layer Aug 17, 2005 Issued
Array ( [id] => 5588813 [patent_doc_number] => 20060038264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-23 [patent_title] => 'Printed circuit board' [patent_app_type] => utility [patent_app_number] => 11/205331 [patent_app_country] => US [patent_app_date] => 2005-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4110 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20060038264.pdf [firstpage_image] =>[orig_patent_app_number] => 11205331 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/205331
Printed circuit board Aug 16, 2005 Abandoned
Array ( [id] => 7053905 [patent_doc_number] => 20050275077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-15 [patent_title] => 'High density chip scale leadframe package and method of manufacturing the package' [patent_app_type] => utility [patent_app_number] => 11/205182 [patent_app_country] => US [patent_app_date] => 2005-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7236 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0275/20050275077.pdf [firstpage_image] =>[orig_patent_app_number] => 11205182 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/205182
High density chip scale leadframe package and method of manufacturing the package Aug 16, 2005 Issued
Array ( [id] => 5823783 [patent_doc_number] => 20060060965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-23 [patent_title] => 'Semiconductor device having a switch circuit' [patent_app_type] => utility [patent_app_number] => 11/203963 [patent_app_country] => US [patent_app_date] => 2005-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 12952 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20060060965.pdf [firstpage_image] =>[orig_patent_app_number] => 11203963 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/203963
Semiconductor device having a switch circuit Aug 15, 2005 Issued
Array ( [id] => 833849 [patent_doc_number] => 07397140 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-08 [patent_title] => 'Chip module' [patent_app_type] => utility [patent_app_number] => 11/206241 [patent_app_country] => US [patent_app_date] => 2005-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2877 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/397/07397140.pdf [firstpage_image] =>[orig_patent_app_number] => 11206241 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/206241
Chip module Aug 15, 2005 Issued
Array ( [id] => 5152124 [patent_doc_number] => 20070035006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-15 [patent_title] => 'Stackable single package and stacked multi-chip assembly' [patent_app_type] => utility [patent_app_number] => 11/204281 [patent_app_country] => US [patent_app_date] => 2005-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2875 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20070035006.pdf [firstpage_image] =>[orig_patent_app_number] => 11204281 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/204281
Stackable single package and stacked multi-chip assembly Aug 14, 2005 Issued
Array ( [id] => 873332 [patent_doc_number] => 07361987 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-22 [patent_title] => 'Circuit device with at least partial packaging and method for forming' [patent_app_type] => utility [patent_app_number] => 11/148691 [patent_app_country] => US [patent_app_date] => 2005-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4156 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/361/07361987.pdf [firstpage_image] =>[orig_patent_app_number] => 11148691 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/148691
Circuit device with at least partial packaging and method for forming Jul 18, 2005 Issued
Array ( [id] => 411987 [patent_doc_number] => 07282791 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-16 [patent_title] => 'Stacked semiconductor device and semiconductor memory module' [patent_app_type] => utility [patent_app_number] => 11/176292 [patent_app_country] => US [patent_app_date] => 2005-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 41 [patent_no_of_words] => 12109 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/282/07282791.pdf [firstpage_image] =>[orig_patent_app_number] => 11176292 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/176292
Stacked semiconductor device and semiconductor memory module Jul 7, 2005 Issued
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