
Jasmine Jhihan B. Clark
Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )
| Most Active Art Unit | 2815 |
| Art Unit(s) | 2815, 2899, 3621, 2816, 2503 |
| Total Applications | 3065 |
| Issued Applications | 2831 |
| Pending Applications | 98 |
| Abandoned Applications | 163 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5054429
[patent_doc_number] => 20070057350
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-15
[patent_title] => 'Semiconductor component and method of assembling the same'
[patent_app_type] => utility
[patent_app_number] => 11/224301
[patent_app_country] => US
[patent_app_date] => 2005-09-13
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[pdf_file] => publications/A1/0057/20070057350.pdf
[firstpage_image] =>[orig_patent_app_number] => 11224301
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/224301 | Semiconductor component and method of assembling the same | Sep 12, 2005 | Issued |
Array
(
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[patent_doc_number] => 20060087045
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[patent_kind] => A1
[patent_issue_date] => 2006-04-27
[patent_title] => 'Substrate having a built-in chip and external connection terminals on both sides and a method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/224821
[patent_app_country] => US
[patent_app_date] => 2005-09-13
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Array
(
[id] => 4876720
[patent_doc_number] => 20080150103
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[patent_kind] => A1
[patent_issue_date] => 2008-06-26
[patent_title] => 'Multi-Die Ic Package and Manufacturing Method'
[patent_app_type] => utility
[patent_app_number] => 11/662431
[patent_app_country] => US
[patent_app_date] => 2005-09-09
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[firstpage_image] =>[orig_patent_app_number] => 11662431
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/662431 | Multi-die IC package and manufacturing method | Sep 8, 2005 | Issued |
Array
(
[id] => 418715
[patent_doc_number] => 07276387
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[patent_issue_date] => 2007-10-02
[patent_title] => 'Castellation wafer level packaging of integrated circuit chips'
[patent_app_type] => utility
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[patent_app_country] => US
[patent_app_date] => 2005-09-07
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Array
(
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[patent_title] => 'Castellation wafer level packaging of integrated circuit chips'
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Array
(
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[patent_issue_date] => 2009-01-13
[patent_title] => 'Electronic device with integrated heat distributor'
[patent_app_type] => utility
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Array
(
[id] => 5180728
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[patent_title] => 'Die pad for semiconductor packages and methods of making and using same'
[patent_app_type] => utility
[patent_app_number] => 11/220761
[patent_app_country] => US
[patent_app_date] => 2005-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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Array
(
[id] => 5708176
[patent_doc_number] => 20060049520
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-09
[patent_title] => 'Semiconductor device mounting structure for reducing thermal stress and warpage'
[patent_app_type] => utility
[patent_app_number] => 11/217292
[patent_app_country] => US
[patent_app_date] => 2005-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
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[firstpage_image] =>[orig_patent_app_number] => 11217292
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/217292 | Semiconductor device mounting structure for reducing thermal stress and warpage | Sep 1, 2005 | Issued |
Array
(
[id] => 5145791
[patent_doc_number] => 20070045845
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[patent_title] => 'Ball grid array interface structure and method'
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[patent_app_number] => 11/216961
[patent_app_country] => US
[patent_app_date] => 2005-08-31
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[firstpage_image] =>[orig_patent_app_number] => 11216961
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/216961 | Ball grid array interface structure and method | Aug 30, 2005 | Abandoned |
Array
(
[id] => 428994
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[patent_title] => 'Semiconductor device and process for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/213882
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Array
(
[id] => 513340
[patent_doc_number] => 07196414
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[patent_title] => 'Semiconductor package with heat sink'
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[firstpage_image] =>[orig_patent_app_number] => 11212182
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/212182 | Semiconductor package with heat sink | Aug 25, 2005 | Issued |
Array
(
[id] => 4992288
[patent_doc_number] => 20070007632
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[patent_title] => 'Optical package with double formed leadframe'
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Array
(
[id] => 840793
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[patent_issue_date] => 2008-06-24
[patent_title] => 'Signal routing on redistribution layer'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/206481 | Signal routing on redistribution layer | Aug 17, 2005 | Issued |
Array
(
[id] => 5588813
[patent_doc_number] => 20060038264
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[patent_title] => 'Printed circuit board'
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[firstpage_image] =>[orig_patent_app_number] => 11205331
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/205331 | Printed circuit board | Aug 16, 2005 | Abandoned |
Array
(
[id] => 7053905
[patent_doc_number] => 20050275077
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Array
(
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Array
(
[id] => 833849
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Array
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Array
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Array
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[firstpage_image] =>[orig_patent_app_number] => 11176292
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/176292 | Stacked semiconductor device and semiconductor memory module | Jul 7, 2005 | Issued |