Jasmine Jhihan B. Clark

Array ( [id] => 5622977 [patent_doc_number] => 20060261482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'Apparatus and method for testing component built in circuit board' [patent_app_type] => utility [patent_app_number] => 11/131741 [patent_app_country] => US [patent_app_date] => 2005-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5081 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20060261482.pdf [firstpage_image] =>[orig_patent_app_number] => 11131741 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5733026 [patent_doc_number] => 20060258143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Method of reducing process steps in metal line protective structure formation' [patent_app_type] => utility [patent_app_number] => 11/131111 [patent_app_country] => US [patent_app_date] => 2005-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2728 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20060258143.pdf [firstpage_image] =>[orig_patent_app_number] => 11131111 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 459723 [patent_doc_number] => 07241643 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-07-10 [patent_title] => 'Wafer level chip scale package' [patent_app_type] => utility [patent_app_number] => 11/126461 [patent_app_country] => US [patent_app_date] => 2005-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 6272 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/241/07241643.pdf [firstpage_image] =>[orig_patent_app_number] => 11126461 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5659234 [patent_doc_number] => 20060249830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'Large die package and method for the fabrication thereof' [patent_app_type] => utility [patent_app_number] => 11/126052 [patent_app_country] => US [patent_app_date] => 2005-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4723 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0249/20060249830.pdf [firstpage_image] =>[orig_patent_app_number] => 11126052 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5268616 [patent_doc_number] => 20090072391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'Structurally-enhanced integrated circuit package and method of manufacture' [patent_app_type] => utility [patent_app_number] => 11/579326 [patent_app_country] => US [patent_app_date] => 2005-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3869 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20090072391.pdf [firstpage_image] =>[orig_patent_app_number] => 11579326 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 807355 [patent_doc_number] => 07420280 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-09-02 [patent_title] => 'Reduced stress under bump metallization structure' [patent_app_type] => utility [patent_app_number] => 11/120841 [patent_app_country] => US [patent_app_date] => 2005-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3226 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/420/07420280.pdf [firstpage_image] =>[orig_patent_app_number] => 11120841 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 530626 [patent_doc_number] => 07183652 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-27 [patent_title] => 'Electronic component and electronic configuration' [patent_app_type] => utility [patent_app_number] => 11/115401 [patent_app_country] => US [patent_app_date] => 2005-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6959 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/183/07183652.pdf [firstpage_image] =>[orig_patent_app_number] => 11115401 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 881192 [patent_doc_number] => 07355273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-08 [patent_title] => 'Semiconductor dice having back side redistribution layer accessed using through-silicon vias, methods' [patent_app_type] => utility [patent_app_number] => 11/110431 [patent_app_country] => US [patent_app_date] => 2005-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7160 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/355/07355273.pdf [firstpage_image] =>[orig_patent_app_number] => 11110431 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 742939 [patent_doc_number] => 07030478 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-18 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/108735 [patent_app_country] => US [patent_app_date] => 2005-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 9371 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/030/07030478.pdf [firstpage_image] =>[orig_patent_app_number] => 11108735 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 642836 [patent_doc_number] => 07122901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-17 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/108711 [patent_app_country] => US [patent_app_date] => 2005-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 6737 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/122/07122901.pdf [firstpage_image] =>[orig_patent_app_number] => 11108711 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6963899 [patent_doc_number] => 20050230796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/105482 [patent_app_country] => US [patent_app_date] => 2005-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 12589 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20050230796.pdf [firstpage_image] =>[orig_patent_app_number] => 11105482 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 547851 [patent_doc_number] => 07166920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-23 [patent_title] => 'Electronic component, mounted structure, electro-optical device, and electronic device' [patent_app_type] => utility [patent_app_number] => 11/103412 [patent_app_country] => US [patent_app_date] => 2005-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5394 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/166/07166920.pdf [firstpage_image] =>[orig_patent_app_number] => 11103412 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6923450 [patent_doc_number] => 20050236705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-27 [patent_title] => 'Wire bonding system and method of use' [patent_app_type] => utility [patent_app_number] => 11/100642 [patent_app_country] => US [patent_app_date] => 2005-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2100 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20050236705.pdf [firstpage_image] =>[orig_patent_app_number] => 11100642 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 642811 [patent_doc_number] => 07122888 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-17 [patent_title] => 'Semiconductor device, electrical inspection method thereof, and electronic apparatus including the semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/091851 [patent_app_country] => US [patent_app_date] => 2005-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 11306 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/122/07122888.pdf [firstpage_image] =>[orig_patent_app_number] => 11091851 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 508098 [patent_doc_number] => 07202567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-10 [patent_title] => 'Semiconductor device and manufacturing method for the same' [patent_app_type] => utility [patent_app_number] => 11/090112 [patent_app_country] => US [patent_app_date] => 2005-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 8012 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/202/07202567.pdf [firstpage_image] =>[orig_patent_app_number] => 11090112 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5634463 [patent_doc_number] => 20060065436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-30 [patent_title] => 'System and method for protecting microelectromechanical systems array using back-plate with non-flat portion' [patent_app_type] => utility [patent_app_number] => 11/090481 [patent_app_country] => US [patent_app_date] => 2005-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11447 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20060065436.pdf [firstpage_image] =>[orig_patent_app_number] => 11090481 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7183503 [patent_doc_number] => 20050161816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/089212 [patent_app_country] => US [patent_app_date] => 2005-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3017 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20050161816.pdf [firstpage_image] =>[orig_patent_app_number] => 11089212 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 646415 [patent_doc_number] => 07119425 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-10 [patent_title] => 'Stacked multi-chip semiconductor package improving connection reliability of stacked chips' [patent_app_type] => utility [patent_app_number] => 11/089361 [patent_app_country] => US [patent_app_date] => 2005-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3442 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/119/07119425.pdf [firstpage_image] =>[orig_patent_app_number] => 11089361 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7595197 [patent_doc_number] => 07626264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-01 [patent_title] => 'Substrate for device bonding and method for manufacturing same' [patent_app_type] => utility [patent_app_number] => 10/593602 [patent_app_country] => US [patent_app_date] => 2005-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 5965 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/626/07626264.pdf [firstpage_image] =>[orig_patent_app_number] => 10593602 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 503314 [patent_doc_number] => 07205652 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-17 [patent_title] => 'Electronic assembly including multiple substrates' [patent_app_type] => utility [patent_app_number] => 11/088101 [patent_app_country] => US [patent_app_date] => 2005-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1939 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/205/07205652.pdf [firstpage_image] =>[orig_patent_app_number] => 11088101 [rel_patent_id] =>[rel_patent_doc_number] =>)