Jason C Olson
Examiner (ID: 1514, Phone: (571)272-7560 , Office: P/3649 )
Most Active Art Unit | 2627 |
Art Unit(s) | OPET, 2688, 2695, 2627, 3649, 2697, 2651 |
Total Applications | 1280 |
Issued Applications | 1069 |
Pending Applications | 5 |
Abandoned Applications | 206 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4507034
[patent_doc_number] => 07920435
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-04-05
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 12/188637
[patent_app_country] => US
[patent_app_date] => 2008-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 3894
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/920/07920435.pdf
[firstpage_image] =>[orig_patent_app_number] => 12188637
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/188637 | Semiconductor memory device | Aug 7, 2008 | Issued |
Array
(
[id] => 5421119
[patent_doc_number] => 20090147574
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-06-11
[patent_title] => 'Flash Memory Device for Determining Most Significant Bit Program'
[patent_app_type] => utility
[patent_app_number] => 12/188057
[patent_app_country] => US
[patent_app_date] => 2008-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5102
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0147/20090147574.pdf
[firstpage_image] =>[orig_patent_app_number] => 12188057
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/188057 | Flash memory device for determining most significant bit program | Aug 6, 2008 | Issued |
Array
(
[id] => 16067
[patent_doc_number] => 07808846
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-10-05
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 12/187803
[patent_app_country] => US
[patent_app_date] => 2008-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 22
[patent_no_of_words] => 27274
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/808/07808846.pdf
[firstpage_image] =>[orig_patent_app_number] => 12187803
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/187803 | Semiconductor memory device | Aug 6, 2008 | Issued |
Array
(
[id] => 4541060
[patent_doc_number] => 07872932
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-01-18
[patent_title] => 'Method of precharging local input/output line and semiconductor memory device using the method'
[patent_app_type] => utility
[patent_app_number] => 12/187269
[patent_app_country] => US
[patent_app_date] => 2008-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 6381
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 347
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/872/07872932.pdf
[firstpage_image] =>[orig_patent_app_number] => 12187269
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/187269 | Method of precharging local input/output line and semiconductor memory device using the method | Aug 5, 2008 | Issued |
Array
(
[id] => 4790786
[patent_doc_number] => 20080291759
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-11-27
[patent_title] => 'APPARATUS AND METHOD OF GENERATING OUTPUT ENABLE SIGNAL FOR SEMICONDUCTOR MEMORY APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 12/185866
[patent_app_country] => US
[patent_app_date] => 2008-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4057
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0291/20080291759.pdf
[firstpage_image] =>[orig_patent_app_number] => 12185866
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/185866 | Apparatus and method of generating output enable signal for semiconductor memory apparatus | Aug 4, 2008 | Issued |
Array
(
[id] => 4582216
[patent_doc_number] => 07830691
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-11-09
[patent_title] => 'Low power content addressable memory'
[patent_app_type] => utility
[patent_app_number] => 12/175272
[patent_app_country] => US
[patent_app_date] => 2008-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 23
[patent_no_of_words] => 19524
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/830/07830691.pdf
[firstpage_image] =>[orig_patent_app_number] => 12175272
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/175272 | Low power content addressable memory | Jul 16, 2008 | Issued |
Array
(
[id] => 4838515
[patent_doc_number] => 20080279000
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-11-13
[patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY'
[patent_app_type] => utility
[patent_app_number] => 12/172889
[patent_app_country] => US
[patent_app_date] => 2008-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 10386
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0279/20080279000.pdf
[firstpage_image] =>[orig_patent_app_number] => 12172889
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/172889 | NONVOLATILE SEMICONDUCTOR MEMORY | Jul 13, 2008 | Abandoned |
Array
(
[id] => 8019763
[patent_doc_number] => 08139390
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-03-20
[patent_title] => 'Mixed data rates in memory devices and systems'
[patent_app_type] => utility
[patent_app_number] => 12/169115
[patent_app_country] => US
[patent_app_date] => 2008-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6314
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/139/08139390.pdf
[firstpage_image] =>[orig_patent_app_number] => 12169115
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/169115 | Mixed data rates in memory devices and systems | Jul 7, 2008 | Issued |
Array
(
[id] => 24618
[patent_doc_number] => 07800936
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-09-21
[patent_title] => 'Latch-based random access memory'
[patent_app_type] => utility
[patent_app_number] => 12/168277
[patent_app_country] => US
[patent_app_date] => 2008-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2936
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 257
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/800/07800936.pdf
[firstpage_image] =>[orig_patent_app_number] => 12168277
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/168277 | Latch-based random access memory | Jul 6, 2008 | Issued |
Array
(
[id] => 4465097
[patent_doc_number] => 07881146
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-02-01
[patent_title] => 'Semiconductor memory apparatus capable of selectively providing decoded row address'
[patent_app_type] => utility
[patent_app_number] => 12/168575
[patent_app_country] => US
[patent_app_date] => 2008-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3401
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/881/07881146.pdf
[firstpage_image] =>[orig_patent_app_number] => 12168575
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/168575 | Semiconductor memory apparatus capable of selectively providing decoded row address | Jul 6, 2008 | Issued |
Array
(
[id] => 7970021
[patent_doc_number] => 07940585
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-05-10
[patent_title] => 'Multi-column decoder stress test circuit'
[patent_app_type] => utility
[patent_app_number] => 12/168611
[patent_app_country] => US
[patent_app_date] => 2008-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 13
[patent_no_of_words] => 7127
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 37
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/940/07940585.pdf
[firstpage_image] =>[orig_patent_app_number] => 12168611
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/168611 | Multi-column decoder stress test circuit | Jul 6, 2008 | Issued |
Array
(
[id] => 35021
[patent_doc_number] => 07791955
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-09-07
[patent_title] => 'Method of erasing a block of memory cells'
[patent_app_type] => utility
[patent_app_number] => 12/168863
[patent_app_country] => US
[patent_app_date] => 2008-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 7059
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/791/07791955.pdf
[firstpage_image] =>[orig_patent_app_number] => 12168863
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/168863 | Method of erasing a block of memory cells | Jul 6, 2008 | Issued |
Array
(
[id] => 4958968
[patent_doc_number] => 20080273392
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-11-06
[patent_title] => 'METHOD OF PROGRAMMING A SELECTED MEMORY CELL'
[patent_app_type] => utility
[patent_app_number] => 12/168858
[patent_app_country] => US
[patent_app_date] => 2008-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7060
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0273/20080273392.pdf
[firstpage_image] =>[orig_patent_app_number] => 12168858
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/168858 | Method of programming a selected memory cell | Jul 6, 2008 | Issued |
Array
(
[id] => 5335768
[patent_doc_number] => 20090052232
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-02-26
[patent_title] => 'METHOD FOR FABRICATING AN INTEGRATED CIRCUIT INCLUDING MEMORY ELEMENT WITH SPATIALLY STABLE MATERIAL'
[patent_app_type] => utility
[patent_app_number] => 12/167853
[patent_app_country] => US
[patent_app_date] => 2008-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 8130
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0052/20090052232.pdf
[firstpage_image] =>[orig_patent_app_number] => 12167853
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/167853 | Method for fabricating an integrated circuit including memory element with spatially stable material | Jul 2, 2008 | Issued |
Array
(
[id] => 4590530
[patent_doc_number] => 07852695
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-12-14
[patent_title] => 'Single-ended differential signal amplification and data reading'
[patent_app_type] => utility
[patent_app_number] => 12/140387
[patent_app_country] => US
[patent_app_date] => 2008-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 1623
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/852/07852695.pdf
[firstpage_image] =>[orig_patent_app_number] => 12140387
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/140387 | Single-ended differential signal amplification and data reading | Jun 16, 2008 | Issued |
Array
(
[id] => 5372853
[patent_doc_number] => 20090310413
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-17
[patent_title] => 'REVERSE ORDER PAGE WRITING IN FLASH MEMORIES'
[patent_app_type] => utility
[patent_app_number] => 12/139545
[patent_app_country] => US
[patent_app_date] => 2008-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8629
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0310/20090310413.pdf
[firstpage_image] =>[orig_patent_app_number] => 12139545
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/139545 | Reverse order page writing in flash memories | Jun 15, 2008 | Issued |
Array
(
[id] => 26207
[patent_doc_number] => 07796460
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-09-14
[patent_title] => 'Nonvolatile semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 12/140071
[patent_app_country] => US
[patent_app_date] => 2008-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 4189
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/796/07796460.pdf
[firstpage_image] =>[orig_patent_app_number] => 12140071
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/140071 | Nonvolatile semiconductor memory device | Jun 15, 2008 | Issued |
Array
(
[id] => 5263609
[patent_doc_number] => 20090116294
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-05-07
[patent_title] => 'METHOD OF PROGRAMMING CELL IN MEMORY AND MEMORY APPARATUS UTILIZING THE METHOD'
[patent_app_type] => utility
[patent_app_number] => 12/138707
[patent_app_country] => US
[patent_app_date] => 2008-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5028
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0116/20090116294.pdf
[firstpage_image] =>[orig_patent_app_number] => 12138707
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/138707 | Method of programming cell in memory and memory apparatus utilizing the method | Jun 12, 2008 | Issued |
Array
(
[id] => 5384352
[patent_doc_number] => 20090225596
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-09-10
[patent_title] => 'NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/138503
[patent_app_country] => US
[patent_app_date] => 2008-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3836
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0225/20090225596.pdf
[firstpage_image] =>[orig_patent_app_number] => 12138503
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/138503 | Non-volatile memory device and method of operating the same | Jun 12, 2008 | Issued |
Array
(
[id] => 4777365
[patent_doc_number] => 20080285363
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-11-20
[patent_title] => 'Self-feedback control pipeline architecture for memory read path applications'
[patent_app_type] => utility
[patent_app_number] => 12/157684
[patent_app_country] => US
[patent_app_date] => 2008-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4058
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0285/20080285363.pdf
[firstpage_image] =>[orig_patent_app_number] => 12157684
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/157684 | Self-feedback control pipeline architecture for memory read path applications | Jun 11, 2008 | Issued |