Jason C Olson

Array ( [id] => 4541126 [patent_doc_number] => 07872940 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-18 [patent_title] => 'Semiconductor memory device and method for testing the same' [patent_app_type] => utility [patent_app_number] => 12/154943 [patent_app_country] => US [patent_app_date] => 2008-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5636 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/872/07872940.pdf [firstpage_image] =>[orig_patent_app_number] => 12154943 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 35047 [patent_doc_number] => 07791963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-07 [patent_title] => 'Semiconductor memory device and operation method thereof' [patent_app_type] => utility [patent_app_number] => 12/154937 [patent_app_country] => US [patent_app_date] => 2008-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6554 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/791/07791963.pdf [firstpage_image] =>[orig_patent_app_number] => 12154937 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4615330 [patent_doc_number] => 07990777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-02 [patent_title] => 'Method, apparatus and system for transmitting data in semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/122755 [patent_app_country] => US [patent_app_date] => 2008-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4084 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/990/07990777.pdf [firstpage_image] =>[orig_patent_app_number] => 12122755 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4777349 [patent_doc_number] => 20080285347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => 'NON-VOLATILE MEMORY DEVICES AND SYSTEMS INCLUDING BAD BLOCKS ADDRESS RE-MAPPED AND METHODS OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/122369 [patent_app_country] => US [patent_app_date] => 2008-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6637 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20080285347.pdf [firstpage_image] =>[orig_patent_app_number] => 12122369 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7556476 [patent_doc_number] => 08068380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-29 [patent_title] => 'Block repair scheme' [patent_app_type] => utility [patent_app_number] => 12/120871 [patent_app_country] => US [patent_app_date] => 2008-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7614 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/068/08068380.pdf [firstpage_image] =>[orig_patent_app_number] => 12120871 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4730347 [patent_doc_number] => 20080209126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'METHOD FOR ACHIEVING VERY HIGH BANDWIDTH BETWEEN THE LEVELS OF A CACHE HIERARCHY IN 3-DIMENSIONAL STRUCTURES, AND A 3-DIMENSIONAL STRUCTURE RESULTING THEREFROM' [patent_app_type] => utility [patent_app_number] => 12/116771 [patent_app_country] => US [patent_app_date] => 2008-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4703 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20080209126.pdf [firstpage_image] =>[orig_patent_app_number] => 12116771 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 304623 [patent_doc_number] => 07535769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-19 [patent_title] => 'Time-dependent compensation currents in non-volatile memory read operations' [patent_app_type] => utility [patent_app_number] => 12/108710 [patent_app_country] => US [patent_app_date] => 2008-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 30 [patent_no_of_words] => 23998 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/535/07535769.pdf [firstpage_image] =>[orig_patent_app_number] => 12108710 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4811926 [patent_doc_number] => 20080192557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'System and method for reducing power consumption during extended refresh periods of dynamic random access memory devices' [patent_app_type] => utility [patent_app_number] => 12/082579 [patent_app_country] => US [patent_app_date] => 2008-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4755 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20080192557.pdf [firstpage_image] =>[orig_patent_app_number] => 12082579 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6564750 [patent_doc_number] => 20100128536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-27 [patent_title] => 'MEMORY CELL, A MEMORY ARRAY AND A METHOD OF PROGRAMMING A MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 12/594595 [patent_app_country] => US [patent_app_date] => 2008-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10089 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20100128536.pdf [firstpage_image] =>[orig_patent_app_number] => 12594595 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7797102 [patent_doc_number] => 08125812 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-28 [patent_title] => 'Method and device for transmitting outgoing useful signals and an outgoing clock signal' [patent_app_type] => utility [patent_app_number] => 12/058899 [patent_app_country] => US [patent_app_date] => 2008-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 11904 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/125/08125812.pdf [firstpage_image] =>[orig_patent_app_number] => 12058899 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4696887 [patent_doc_number] => 20080219071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'Data flow scheme for low power DRAM' [patent_app_type] => utility [patent_app_number] => 12/079446 [patent_app_country] => US [patent_app_date] => 2008-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3348 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20080219071.pdf [firstpage_image] =>[orig_patent_app_number] => 12079446 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4601687 [patent_doc_number] => 07978525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-12 [patent_title] => 'Data flow scheme for low power DRAM' [patent_app_type] => utility [patent_app_number] => 12/079512 [patent_app_country] => US [patent_app_date] => 2008-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3365 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/978/07978525.pdf [firstpage_image] =>[orig_patent_app_number] => 12079512 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 374270 [patent_doc_number] => 07474576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-06 [patent_title] => 'Repairing Advanced-Memory Buffer (AMB) with redundant memory buffer for repairing DRAM on a fully-buffered memory-module' [patent_app_type] => utility [patent_app_number] => 12/053261 [patent_app_country] => US [patent_app_date] => 2008-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5782 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/474/07474576.pdf [firstpage_image] =>[orig_patent_app_number] => 12053261 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4584551 [patent_doc_number] => 07826269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Flash memory device and method for driving the same' [patent_app_type] => utility [patent_app_number] => 12/052003 [patent_app_country] => US [patent_app_date] => 2008-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5898 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/826/07826269.pdf [firstpage_image] =>[orig_patent_app_number] => 12052003 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4926219 [patent_doc_number] => 20080165582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-10 [patent_title] => 'Scalable Electrically Eraseable And Programmable Memory' [patent_app_type] => utility [patent_app_number] => 12/050491 [patent_app_country] => US [patent_app_date] => 2008-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 7498 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20080165582.pdf [firstpage_image] =>[orig_patent_app_number] => 12050491 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6348593 [patent_doc_number] => 20100085814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-08 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE' [patent_app_type] => utility [patent_app_number] => 12/532879 [patent_app_country] => US [patent_app_date] => 2008-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11033 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20100085814.pdf [firstpage_image] =>[orig_patent_app_number] => 12532879 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4818335 [patent_doc_number] => 20080225594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array' [patent_app_type] => utility [patent_app_number] => 12/075677 [patent_app_country] => US [patent_app_date] => 2008-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 20491 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20080225594.pdf [firstpage_image] =>[orig_patent_app_number] => 12075677 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4674750 [patent_doc_number] => 20080212378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'DATA LATCH CONTROLLER OF SYNCHRONOUS MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/047429 [patent_app_country] => US [patent_app_date] => 2008-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3099 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20080212378.pdf [firstpage_image] =>[orig_patent_app_number] => 12047429 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4662264 [patent_doc_number] => 20080253171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-16 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/039585 [patent_app_country] => US [patent_app_date] => 2008-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4267 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20080253171.pdf [firstpage_image] =>[orig_patent_app_number] => 12039585 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 24661 [patent_doc_number] => 07800960 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-21 [patent_title] => 'Voltage generator for nonvolatile memory and writing and erasing method of nonvolatile memory' [patent_app_type] => utility [patent_app_number] => 12/071765 [patent_app_country] => US [patent_app_date] => 2008-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 33 [patent_no_of_words] => 12148 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/800/07800960.pdf [firstpage_image] =>[orig_patent_app_number] => 12071765 [rel_patent_id] =>[rel_patent_doc_number] =>)