Jason C Olson

Array ( [id] => 26181 [patent_doc_number] => 07796444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-14 [patent_title] => 'Concurrent programming of non-volatile memory' [patent_app_type] => utility [patent_app_number] => 11/936086 [patent_app_country] => US [patent_app_date] => 2007-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 10892 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/796/07796444.pdf [firstpage_image] =>[orig_patent_app_number] => 11936086 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5263598 [patent_doc_number] => 20090116283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'Controlling a memory device responsive to degradation' [patent_app_type] => utility [patent_app_number] => 11/983241 [patent_app_country] => US [patent_app_date] => 2007-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4159 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20090116283.pdf [firstpage_image] =>[orig_patent_app_number] => 11983241 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 264747 [patent_doc_number] => 07570518 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-04 [patent_title] => 'Concurrent programming of non-volatile memory' [patent_app_type] => utility [patent_app_number] => 11/936084 [patent_app_country] => US [patent_app_date] => 2007-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 10893 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/570/07570518.pdf [firstpage_image] =>[orig_patent_app_number] => 11936084 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4565018 [patent_doc_number] => 07821835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-26 [patent_title] => 'Concurrent programming of non-volatile memory' [patent_app_type] => utility [patent_app_number] => 11/936081 [patent_app_country] => US [patent_app_date] => 2007-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 10854 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/821/07821835.pdf [firstpage_image] =>[orig_patent_app_number] => 11936081 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4898046 [patent_doc_number] => 20080117659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-22 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/935931 [patent_app_country] => US [patent_app_date] => 2007-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5014 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20080117659.pdf [firstpage_image] =>[orig_patent_app_number] => 11935931 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7980087 [patent_doc_number] => 08072796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-06 [patent_title] => 'Memory with five-transistor bit cells and associated control circuit' [patent_app_type] => utility [patent_app_number] => 11/929337 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5103 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/072/08072796.pdf [firstpage_image] =>[orig_patent_app_number] => 11929337 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5329266 [patent_doc_number] => 20090109743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'MULTILEVEL MEMORY CELL OPERATION' [patent_app_type] => utility [patent_app_number] => 11/924793 [patent_app_country] => US [patent_app_date] => 2007-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14391 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20090109743.pdf [firstpage_image] =>[orig_patent_app_number] => 11924793 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5329257 [patent_doc_number] => 20090109734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'NON-VOLATILE SRAM CELL' [patent_app_type] => utility [patent_app_number] => 11/924801 [patent_app_country] => US [patent_app_date] => 2007-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6779 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20090109734.pdf [firstpage_image] =>[orig_patent_app_number] => 11924801 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4914307 [patent_doc_number] => 20080094907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'FLASH MEMORIES WITH ADAPTIVE REFERENCE VOLTAGES' [patent_app_type] => utility [patent_app_number] => 11/923677 [patent_app_country] => US [patent_app_date] => 2007-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5749 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20080094907.pdf [firstpage_image] =>[orig_patent_app_number] => 11923677 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 133997 [patent_doc_number] => 07701744 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-20 [patent_title] => 'Method of arranging fuses in a fuse box of a semiconductor memory device and a semiconductor memory device including such an arrangement' [patent_app_type] => utility [patent_app_number] => 11/976125 [patent_app_country] => US [patent_app_date] => 2007-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4411 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/701/07701744.pdf [firstpage_image] =>[orig_patent_app_number] => 11976125 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 94671 [patent_doc_number] => 07738281 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-15 [patent_title] => 'Semiconductor storage device' [patent_app_type] => utility [patent_app_number] => 11/907741 [patent_app_country] => US [patent_app_date] => 2007-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6873 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/738/07738281.pdf [firstpage_image] =>[orig_patent_app_number] => 11907741 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4763839 [patent_doc_number] => 20080175050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-24 [patent_title] => 'PFET NONVOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 11/865777 [patent_app_country] => US [patent_app_date] => 2007-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7063 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20080175050.pdf [firstpage_image] =>[orig_patent_app_number] => 11865777 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4582413 [patent_doc_number] => 07830707 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-09 [patent_title] => 'Method of reading dual-bit memory cell' [patent_app_type] => utility [patent_app_number] => 11/905211 [patent_app_country] => US [patent_app_date] => 2007-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 3724 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/830/07830707.pdf [firstpage_image] =>[orig_patent_app_number] => 11905211 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 842120 [patent_doc_number] => 07391636 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-24 [patent_title] => 'Semiconductor memory device and arrangement method thereof' [patent_app_type] => utility [patent_app_number] => 11/863151 [patent_app_country] => US [patent_app_date] => 2007-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12252 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/391/07391636.pdf [firstpage_image] =>[orig_patent_app_number] => 11863151 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4801810 [patent_doc_number] => 20080013397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND ARRANGEMENT METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/863141 [patent_app_country] => US [patent_app_date] => 2007-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12250 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20080013397.pdf [firstpage_image] =>[orig_patent_app_number] => 11863141 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4937595 [patent_doc_number] => 20080074912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-27 [patent_title] => 'ANALOG MEMORY' [patent_app_type] => utility [patent_app_number] => 11/861437 [patent_app_country] => US [patent_app_date] => 2007-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4983 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20080074912.pdf [firstpage_image] =>[orig_patent_app_number] => 11861437 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 161365 [patent_doc_number] => 07675792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-09 [patent_title] => 'Generating reference currents compensated for process variation in non-volatile memories' [patent_app_type] => utility [patent_app_number] => 11/904071 [patent_app_country] => US [patent_app_date] => 2007-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3345 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/675/07675792.pdf [firstpage_image] =>[orig_patent_app_number] => 11904071 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 66448 [patent_doc_number] => 07760547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-20 [patent_title] => 'Offset non-volatile storage' [patent_app_type] => utility [patent_app_number] => 11/861135 [patent_app_country] => US [patent_app_date] => 2007-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 6799 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/760/07760547.pdf [firstpage_image] =>[orig_patent_app_number] => 11861135 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5507072 [patent_doc_number] => 20090080279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'STRUCTURE TO SHARE INTERNALLY GENERATED VOLTAGES BETWEEN CHIPS IN MCP' [patent_app_type] => utility [patent_app_number] => 11/860977 [patent_app_country] => US [patent_app_date] => 2007-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2063 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20090080279.pdf [firstpage_image] =>[orig_patent_app_number] => 11860977 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4796414 [patent_doc_number] => 20080008000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-10 [patent_title] => 'REVERSE COUPLING EFFECT WITH TIMING INFORMATION' [patent_app_type] => utility [patent_app_number] => 11/858902 [patent_app_country] => US [patent_app_date] => 2007-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11973 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20080008000.pdf [firstpage_image] =>[orig_patent_app_number] => 11858902 [rel_patent_id] =>[rel_patent_doc_number] =>)