Jason C Olson

Array ( [id] => 5229437 [patent_doc_number] => 20070291544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-20 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/806961 [patent_app_country] => US [patent_app_date] => 2007-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4557 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20070291544.pdf [firstpage_image] =>[orig_patent_app_number] => 11806961 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4784104 [patent_doc_number] => 20080137433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'Methods and apparatuses for trimming reference cells in semiconductor memory devices' [patent_app_type] => utility [patent_app_number] => 11/806587 [patent_app_country] => US [patent_app_date] => 2007-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4440 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20080137433.pdf [firstpage_image] =>[orig_patent_app_number] => 11806587 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5084073 [patent_doc_number] => 20070274124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-29 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE WITH IMPROVED RESISTANCE TO DISTURBANCE AND IMPROVED WRITING CHARACTERISTIC' [patent_app_type] => utility [patent_app_number] => 11/753111 [patent_app_country] => US [patent_app_date] => 2007-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8077 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0274/20070274124.pdf [firstpage_image] =>[orig_patent_app_number] => 11753111 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4777360 [patent_doc_number] => 20080285358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => 'Method and circuit for stressing upper level interconnects in semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/798513 [patent_app_country] => US [patent_app_date] => 2007-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4259 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20080285358.pdf [firstpage_image] =>[orig_patent_app_number] => 11798513 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5026634 [patent_doc_number] => 20070268080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-22 [patent_title] => 'Oscillator circuit generating oscillating signal having stable cycle' [patent_app_type] => utility [patent_app_number] => 11/798485 [patent_app_country] => US [patent_app_date] => 2007-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7336 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20070268080.pdf [firstpage_image] =>[orig_patent_app_number] => 11798485 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5130033 [patent_doc_number] => 20070206430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-06 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 11/747552 [patent_app_country] => US [patent_app_date] => 2007-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6046 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20070206430.pdf [firstpage_image] =>[orig_patent_app_number] => 11747552 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5130023 [patent_doc_number] => 20070206420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-06 [patent_title] => 'MODE SELECTION IN A FLASH MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/746913 [patent_app_country] => US [patent_app_date] => 2007-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3017 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20070206420.pdf [firstpage_image] =>[orig_patent_app_number] => 11746913 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7598896 [patent_doc_number] => 07583553 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-01 [patent_title] => 'Semiconductor memory and refresh cycle control method' [patent_app_type] => utility [patent_app_number] => 11/797817 [patent_app_country] => US [patent_app_date] => 2007-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 6470 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/583/07583553.pdf [firstpage_image] =>[orig_patent_app_number] => 11797817 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5111717 [patent_doc_number] => 20070195632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Semiconductor memory device having a global data bus' [patent_app_type] => utility [patent_app_number] => 11/789257 [patent_app_country] => US [patent_app_date] => 2007-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4459 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20070195632.pdf [firstpage_image] =>[orig_patent_app_number] => 11789257 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4661445 [patent_doc_number] => 20080252352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-16 [patent_title] => 'System and Method for Using a DLL for Signal Timing Control in an eDRAM' [patent_app_type] => utility [patent_app_number] => 11/735455 [patent_app_country] => US [patent_app_date] => 2007-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1860 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0252/20080252352.pdf [firstpage_image] =>[orig_patent_app_number] => 11735455 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5012577 [patent_doc_number] => 20070283056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'CONTROL DEVICE FOR CONTROLLING A BUFFER MEMORY' [patent_app_type] => utility [patent_app_number] => 11/735429 [patent_app_country] => US [patent_app_date] => 2007-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6704 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20070283056.pdf [firstpage_image] =>[orig_patent_app_number] => 11735429 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 367503 [patent_doc_number] => 07480188 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-20 [patent_title] => 'Memory Access apparatus' [patent_app_type] => utility [patent_app_number] => 11/734749 [patent_app_country] => US [patent_app_date] => 2007-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 7873 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/480/07480188.pdf [firstpage_image] =>[orig_patent_app_number] => 11734749 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 279039 [patent_doc_number] => 07558121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-07 [patent_title] => 'Flash memory device and smart card including the same' [patent_app_type] => utility [patent_app_number] => 11/694473 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6461 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/558/07558121.pdf [firstpage_image] =>[orig_patent_app_number] => 11694473 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5044797 [patent_doc_number] => 20070263469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-15 [patent_title] => 'Two Levels of Voltage Regulation Supplied for Logic and Data Programming Voltage of a Memory Device' [patent_app_type] => utility [patent_app_number] => 11/694763 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 17373 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20070263469.pdf [firstpage_image] =>[orig_patent_app_number] => 11694763 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 364787 [patent_doc_number] => 07483283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-27 [patent_title] => 'Apparatus for efficient streaming data access on reconfigurable hardware and method for automatic generation thereof' [patent_app_type] => utility [patent_app_number] => 11/694401 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 7847 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/483/07483283.pdf [firstpage_image] =>[orig_patent_app_number] => 11694401 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5044782 [patent_doc_number] => 20070263454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-15 [patent_title] => 'Maintenance Operations for Multi-Level Data Storage Cells' [patent_app_type] => utility [patent_app_number] => 11/694739 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 18488 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20070263454.pdf [firstpage_image] =>[orig_patent_app_number] => 11694739 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5158680 [patent_doc_number] => 20070171724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'Counteracting overtunneling in nonvolatile memory cells' [patent_app_type] => utility [patent_app_number] => 11/731228 [patent_app_country] => US [patent_app_date] => 2007-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 6678 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20070171724.pdf [firstpage_image] =>[orig_patent_app_number] => 11731228 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5218574 [patent_doc_number] => 20070159885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-12 [patent_title] => 'On-Chip Data Grouping and Alignment' [patent_app_type] => utility [patent_app_number] => 11/690253 [patent_app_country] => US [patent_app_date] => 2007-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7127 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20070159885.pdf [firstpage_image] =>[orig_patent_app_number] => 11690253 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4891261 [patent_doc_number] => 20080100358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'Counter control signal generating circuit' [patent_app_type] => utility [patent_app_number] => 11/728095 [patent_app_country] => US [patent_app_date] => 2007-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8654 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20080100358.pdf [firstpage_image] =>[orig_patent_app_number] => 11728095 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 161350 [patent_doc_number] => 07675785 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-09 [patent_title] => 'Semiconductor storage device' [patent_app_type] => utility [patent_app_number] => 11/717666 [patent_app_country] => US [patent_app_date] => 2007-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5591 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/675/07675785.pdf [firstpage_image] =>[orig_patent_app_number] => 11717666 [rel_patent_id] =>[rel_patent_doc_number] =>)