Jason C Olson
Examiner (ID: 1514, Phone: (571)272-7560 , Office: P/3649 )
Most Active Art Unit | 2627 |
Art Unit(s) | OPET, 2688, 2695, 2627, 3649, 2697, 2651 |
Total Applications | 1280 |
Issued Applications | 1069 |
Pending Applications | 5 |
Abandoned Applications | 206 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 597339
[patent_doc_number] => 07436710
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[patent_title] => 'EEPROM memory device with cell having NMOS in a P pocket as a control gate, PMOS program/erase transistor, and PMOS access transistor in a common well'
[patent_app_type] => utility
[patent_app_number] => 11/685111
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Array
(
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[patent_doc_number] => 07663953
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[patent_issue_date] => 2010-02-16
[patent_title] => 'Method for high speed sensing for extra low voltage DRAM'
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Array
(
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[patent_title] => 'Method for increasing retention time in DRAM'
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Array
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[patent_issue_date] => 2010-04-20
[patent_title] => 'Nonvolatile semiconductor memory device'
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Array
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[patent_title] => 'READ-ONLY MEMORY USING LINEAR PASSIVE ELEMENTS'
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/676821 | Memory cell structure of SRAM | Feb 19, 2007 | Issued |
Array
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Array
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Array
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[id] => 5111669
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[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE'
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Array
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Array
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[id] => 4763857
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[patent_title] => 'TEMPERATURE DEPENDENT BACK-BIAS FOR A MEMORY ARRAY'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/624355 | Temperature dependent back-bias for a memory array | Jan 17, 2007 | Issued |
Array
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Array
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/613379 | Method and apparatus for adaptive memory cell overerase compensation | Dec 19, 2006 | Issued |
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/613325 | Hybrid solid-state memory system having volatile and non-volatile memory | Dec 19, 2006 | Issued |
Array
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