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Jason Crawford

Examiner (ID: 13566)

Most Active Art Unit
2844
Art Unit(s)
2819, 2844
Total Applications
1814
Issued Applications
1590
Pending Applications
83
Abandoned Applications
183

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19605676 [patent_doc_number] => 20240396556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => LOGIC FABRIC BASED ON MICROSECTOR INFRASTRUCTURE [patent_app_type] => utility [patent_app_number] => 18/795146 [patent_app_country] => US [patent_app_date] => 2024-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11029 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18795146 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/795146
LOGIC FABRIC BASED ON MICROSECTOR INFRASTRUCTURE Aug 4, 2024 Pending
Array ( [id] => 19576392 [patent_doc_number] => 20240380684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => FPGA NEIGHBOR OUTPUT MUX DIRECT CONNECTIONS TO MINIMIZE ROUTING HOPS [patent_app_type] => utility [patent_app_number] => 18/782656 [patent_app_country] => US [patent_app_date] => 2024-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5723 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18782656 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/782656
FPGA NEIGHBOR OUTPUT MUX DIRECT CONNECTIONS TO MINIMIZE ROUTING HOPS Jul 23, 2024 Pending
Array ( [id] => 19576392 [patent_doc_number] => 20240380684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => FPGA NEIGHBOR OUTPUT MUX DIRECT CONNECTIONS TO MINIMIZE ROUTING HOPS [patent_app_type] => utility [patent_app_number] => 18/782656 [patent_app_country] => US [patent_app_date] => 2024-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5723 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18782656 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/782656
FPGA NEIGHBOR OUTPUT MUX DIRECT CONNECTIONS TO MINIMIZE ROUTING HOPS Jul 23, 2024 Pending
Array ( [id] => 19575811 [patent_doc_number] => 20240380103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => ELECTRONIC DEVICE COMPRISING ANTENNA [patent_app_type] => utility [patent_app_number] => 18/781686 [patent_app_country] => US [patent_app_date] => 2024-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17204 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18781686 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/781686
ELECTRONIC DEVICE COMPRISING ANTENNA Jul 22, 2024 Pending
Array ( [id] => 19727673 [patent_doc_number] => 20250030424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => CMOS-TO-CML CONVERTER, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/778139 [patent_app_country] => US [patent_app_date] => 2024-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8646 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18778139 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/778139
CMOS-TO-CML CONVERTER, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND ELECTRONIC DEVICE Jul 18, 2024 Pending
Array ( [id] => 20088566 [patent_doc_number] => 20250218502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => RTT TRIM METHOD [patent_app_type] => utility [patent_app_number] => 18/760587 [patent_app_country] => US [patent_app_date] => 2024-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5032 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18760587 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/760587
RTT TRIM METHOD Jun 30, 2024 Pending
Array ( [id] => 20088566 [patent_doc_number] => 20250218502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => RTT TRIM METHOD [patent_app_type] => utility [patent_app_number] => 18/760587 [patent_app_country] => US [patent_app_date] => 2024-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5032 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18760587 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/760587
RTT TRIM METHOD Jun 30, 2024 Pending
Array ( [id] => 20284658 [patent_doc_number] => 20250309900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => LOGIC GATE CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/745071 [patent_app_country] => US [patent_app_date] => 2024-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18745071 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/745071
LOGIC GATE CIRCUIT Jun 16, 2024 Pending
Array ( [id] => 19560471 [patent_doc_number] => 20240372263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => DISTRIBUTED MONOPOLE ANTENNA FOR ENHANCED CROSS-BODY LINK [patent_app_type] => utility [patent_app_number] => 18/670406 [patent_app_country] => US [patent_app_date] => 2024-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8762 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18670406 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/670406
Distributed monopole antenna for enhanced cross-body link May 20, 2024 Issued
Array ( [id] => 19453281 [patent_doc_number] => 20240313411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => WAVEGUIDES AND WAVEGUIDE SENSORS WITH SIGNAL-IMPROVING GROOVES AND/OR SLOTS [patent_app_type] => utility [patent_app_number] => 18/670711 [patent_app_country] => US [patent_app_date] => 2024-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11640 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18670711 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/670711
WAVEGUIDES AND WAVEGUIDE SENSORS WITH SIGNAL-IMPROVING GROOVES AND/OR SLOTS May 20, 2024 Pending
Array ( [id] => 20368118 [patent_doc_number] => 20250357930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-20 [patent_title] => CAPACITANCE SENSOR ARRAY CHIP WITH PROGRAMMABLE FUSION PIXELS, SAMPLING DEVICE THEREOF AND CONTROLLING SYSTEM THEREOF [patent_app_type] => utility [patent_app_number] => 18/668308 [patent_app_country] => US [patent_app_date] => 2024-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18668308 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/668308
CAPACITANCE SENSOR ARRAY CHIP WITH PROGRAMMABLE FUSION PIXELS, SAMPLING DEVICE THEREOF AND CONTROLLING SYSTEM THEREOF May 19, 2024 Pending
Array ( [id] => 20368118 [patent_doc_number] => 20250357930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-20 [patent_title] => CAPACITANCE SENSOR ARRAY CHIP WITH PROGRAMMABLE FUSION PIXELS, SAMPLING DEVICE THEREOF AND CONTROLLING SYSTEM THEREOF [patent_app_type] => utility [patent_app_number] => 18/668308 [patent_app_country] => US [patent_app_date] => 2024-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18668308 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/668308
CAPACITANCE SENSOR ARRAY CHIP WITH PROGRAMMABLE FUSION PIXELS, SAMPLING DEVICE THEREOF AND CONTROLLING SYSTEM THEREOF May 19, 2024 Pending
Array ( [id] => 19436801 [patent_doc_number] => 20240305299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => IC WITH FIRST AND SECOND FUNCTIONAL CIRCUITS COUPLING ONLY FIRST CIRCUITS TO OUTPUT BOND PADS [patent_app_type] => utility [patent_app_number] => 18/666135 [patent_app_country] => US [patent_app_date] => 2024-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10875 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18666135 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/666135
IC WITH FIRST AND SECOND FUNCTIONAL CIRCUITS COUPLING ONLY FIRST CIRCUITS TO OUTPUT BOND PADS May 15, 2024 Pending
Array ( [id] => 19436801 [patent_doc_number] => 20240305299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => IC WITH FIRST AND SECOND FUNCTIONAL CIRCUITS COUPLING ONLY FIRST CIRCUITS TO OUTPUT BOND PADS [patent_app_type] => utility [patent_app_number] => 18/666135 [patent_app_country] => US [patent_app_date] => 2024-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10875 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18666135 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/666135
IC WITH FIRST AND SECOND FUNCTIONAL CIRCUITS COUPLING ONLY FIRST CIRCUITS TO OUTPUT BOND PADS May 15, 2024 Pending
Array ( [id] => 20082423 [patent_doc_number] => 12356519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Load control device for a light-emitting diode light source [patent_app_type] => utility [patent_app_number] => 18/663255 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 6444 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663255 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663255
Load control device for a light-emitting diode light source May 13, 2024 Issued
Array ( [id] => 20082423 [patent_doc_number] => 12356519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Load control device for a light-emitting diode light source [patent_app_type] => utility [patent_app_number] => 18/663255 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 6444 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663255 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663255
Load control device for a light-emitting diode light source May 13, 2024 Issued
Array ( [id] => 20339428 [patent_doc_number] => 20250343548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-06 [patent_title] => BLANKING PERIODS FOR SAFELY EXECUTING EXTERNAL TRISTATE REQUESTS [patent_app_type] => utility [patent_app_number] => 18/656354 [patent_app_country] => US [patent_app_date] => 2024-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1197 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18656354 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/656354
BLANKING PERIODS FOR SAFELY EXECUTING EXTERNAL TRISTATE REQUESTS May 5, 2024 Pending
Array ( [id] => 19714428 [patent_doc_number] => 20250024570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => SYSTEMS AND METHODS FOR CONTROLLING POWER FACTORS OF LED LIGHTING SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/639870 [patent_app_country] => US [patent_app_date] => 2024-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18526 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18639870 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/639870
Systems and methods for controlling power factors of LED lighting systems Apr 17, 2024 Issued
Array ( [id] => 19365010 [patent_doc_number] => 20240267044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => GLITCH PREVENTING INPUT/OUTPUT CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/637252 [patent_app_country] => US [patent_app_date] => 2024-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8498 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18637252 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/637252
Glitch preventing input/output circuits Apr 15, 2024 Issued
Array ( [id] => 20346247 [patent_doc_number] => 12469982 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Base station antennas having an active antenna module(s) and related devices and methods [patent_app_type] => utility [patent_app_number] => 18/630425 [patent_app_country] => US [patent_app_date] => 2024-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 46 [patent_no_of_words] => 8661 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18630425 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/630425
Base station antennas having an active antenna module(s) and related devices and methods Apr 8, 2024 Issued
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