Jason Lappas

Array ( [id] => 19123400 [patent_doc_number] => 11967394 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Memory arrays employing flying bit lines to increase effective bit line length for supporting higher performance, increased memory density, and related methods [patent_app_type] => utility [patent_app_number] => 17/836634 [patent_app_country] => US [patent_app_date] => 2022-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 11643 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17836634 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17886161 [patent_doc_number] => 20220301638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => SELECTIVE OVERDRIVE OF SUPPLY VOLTAGE TO PRIMARY SWITCH FOR PROGRAMMING MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/835185 [patent_app_country] => US [patent_app_date] => 2022-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8700 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17835185 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18935219 [patent_doc_number] => 11887657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Amplifier circuit, control method, and memory [patent_app_type] => utility [patent_app_number] => 17/805927 [patent_app_country] => US [patent_app_date] => 2022-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 6050 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17805927 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18820798 [patent_doc_number] => 20230395139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => MEMORY WITH DOUBLE REDUNDANCY [patent_app_type] => utility [patent_app_number] => 17/833852 [patent_app_country] => US [patent_app_date] => 2022-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10282 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17833852 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17870445 [patent_doc_number] => 20220293182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => ESTIMATING RESISTANCE-CAPACITANCE TIME CONSTANT OF ELECTRICAL CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/832117 [patent_app_country] => US [patent_app_date] => 2022-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7292 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17832117 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19487068 [patent_doc_number] => 12106792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-01 [patent_title] => Apparatuses and methods for partial array self refresh masking [patent_app_type] => utility [patent_app_number] => 17/829096 [patent_app_country] => US [patent_app_date] => 2022-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8664 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17829096 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18815096 [patent_doc_number] => 20230389434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => MAGNETO-RESISTIVE RANDOM ACCESS MEMORY WITH HEMISPHERICAL TOP ELECTRODE [patent_app_type] => utility [patent_app_number] => 17/804795 [patent_app_country] => US [patent_app_date] => 2022-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5835 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17804795 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18080749 [patent_doc_number] => 20220406361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => MEMORY DEVICE INCLUDING SUB WORD LINE DRIVING CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/828200 [patent_app_country] => US [patent_app_date] => 2022-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9382 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17828200 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18789036 [patent_doc_number] => 20230377646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => DIFFERENTIAL SUBTHRESHOLD READ OF MEMORY CELL PAIR IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/748666 [patent_app_country] => US [patent_app_date] => 2022-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12169 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17748666 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18774001 [patent_doc_number] => 20230368831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => MEMORY CELL SENSING USING TWO STEP WORD LINE ENABLING [patent_app_type] => utility [patent_app_number] => 17/740528 [patent_app_country] => US [patent_app_date] => 2022-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8140 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17740528 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19062917 [patent_doc_number] => 11942162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Memory device and a method for operating the same [patent_app_type] => utility [patent_app_number] => 17/736250 [patent_app_country] => US [patent_app_date] => 2022-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7095 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17736250 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18008179 [patent_doc_number] => 20220366946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => SEMICONDUCTOR DEVICE PERFORMING A MULTIPLICATION AND ACCUMULATION OPERATION [patent_app_type] => utility [patent_app_number] => 17/732272 [patent_app_country] => US [patent_app_date] => 2022-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4793 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17732272 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20581200 [patent_doc_number] => 12573454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-10 [patent_title] => Power efficient array discharge for program boosting [patent_app_type] => utility [patent_app_number] => 17/732117 [patent_app_country] => US [patent_app_date] => 2022-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17732117 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18950750 [patent_doc_number] => 11894052 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Compensated analog computation for an in-memory computation system [patent_app_type] => utility [patent_app_number] => 17/718908 [patent_app_country] => US [patent_app_date] => 2022-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 27 [patent_no_of_words] => 14902 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718908 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18696075 [patent_doc_number] => 20230326506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => FIRST FIRE AND COLD START IN MEMORIES WITH THRESHOLD SWITCHING SELECTORS [patent_app_type] => utility [patent_app_number] => 17/718759 [patent_app_country] => US [patent_app_date] => 2022-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22905 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718759 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17764539 [patent_doc_number] => 20220238152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => PERFORMING AN ON DEMAND REFRESH OPERATION OF A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 17/718279 [patent_app_country] => US [patent_app_date] => 2022-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10083 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718279 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19459947 [patent_doc_number] => 12100449 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-09-24 [patent_title] => Differential programming of two-terminal resistive switching memory with intrinsic error suppression [patent_app_type] => utility [patent_app_number] => 17/710809 [patent_app_country] => US [patent_app_date] => 2022-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 18582 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17710809 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18364159 [patent_doc_number] => 20230145750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => NONVOLATILE MEMORY AND STORAGE DEVICE INCLUDING SAME [patent_app_type] => utility [patent_app_number] => 17/706097 [patent_app_country] => US [patent_app_date] => 2022-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11832 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17706097 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18935215 [patent_doc_number] => 11887653 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Memory devices [patent_app_type] => utility [patent_app_number] => 17/705915 [patent_app_country] => US [patent_app_date] => 2022-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12453 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17705915 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18166866 [patent_doc_number] => 20230033472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => MEMORY AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/705306 [patent_app_country] => US [patent_app_date] => 2022-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9578 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17705306 [rel_patent_id] =>[rel_patent_doc_number] =>)