Search

Jason Lappas

Examiner (ID: 3968, Phone: (571)270-1272 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
1390
Issued Applications
1293
Pending Applications
55
Abandoned Applications
64

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16995174 [patent_doc_number] => 20210233594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => SELECT GATE MAINTENANCE IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 17/301743 [patent_app_country] => US [patent_app_date] => 2021-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8691 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17301743 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/301743
Select gate maintenance in a memory sub-system Apr 12, 2021 Issued
Array ( [id] => 16981180 [patent_doc_number] => 20210225417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => On-Die Termination of Address and Command Signals [patent_app_type] => utility [patent_app_number] => 17/222388 [patent_app_country] => US [patent_app_date] => 2021-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3698 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17222388 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/222388
On-die termination of address and command signals Apr 4, 2021 Issued
Array ( [id] => 16965982 [patent_doc_number] => 20210217481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING A MEMORY CELL ARRAY AND A CONTROL CIRCUIT APPLYING A READING VOLTAGE [patent_app_type] => utility [patent_app_number] => 17/219003 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10834 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17219003 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/219003
Nonvolatile semiconductor memory device including a memory cell array and a control circuit applying a reading voltage Mar 30, 2021 Issued
Array ( [id] => 19444252 [patent_doc_number] => 12094538 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Architecture and method for NAND memory operation [patent_app_type] => utility [patent_app_number] => 17/215005 [patent_app_country] => US [patent_app_date] => 2021-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7331 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17215005 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/215005
Architecture and method for NAND memory operation Mar 28, 2021 Issued
Array ( [id] => 16965973 [patent_doc_number] => 20210217472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => VARIABLE RESISTIVE MEMORY DEVICE AND METHOD OF DRIVING A VARIABLE RESISTIVE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/214592 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10336 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17214592 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/214592
Variable resistive memory device and method of driving a variable resistive memory device Mar 25, 2021 Issued
Array ( [id] => 17757988 [patent_doc_number] => 11398286 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-07-26 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/213487 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10754 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17213487 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/213487
Semiconductor memory device Mar 25, 2021 Issued
Array ( [id] => 18766747 [patent_doc_number] => 11817154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Optimized threshold translation from serialized pipeline [patent_app_type] => utility [patent_app_number] => 17/210428 [patent_app_country] => US [patent_app_date] => 2021-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12411 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17210428 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/210428
Optimized threshold translation from serialized pipeline Mar 22, 2021 Issued
Array ( [id] => 16951438 [patent_doc_number] => 20210210130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => MEMORY MANAGEMENT FOR CHARGE LEAKAGE IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/208470 [patent_app_country] => US [patent_app_date] => 2021-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 33503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17208470 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/208470
Memory management for charge leakage in a memory device Mar 21, 2021 Issued
Array ( [id] => 17846796 [patent_doc_number] => 11436169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-06 [patent_title] => Individually addressing memory devices disconnected from a data bus [patent_app_type] => utility [patent_app_number] => 17/207561 [patent_app_country] => US [patent_app_date] => 2021-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3441 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17207561 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/207561
Individually addressing memory devices disconnected from a data bus Mar 18, 2021 Issued
Array ( [id] => 17878368 [patent_doc_number] => 11450389 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Non-volatile memory device and an operation method thereof [patent_app_type] => utility [patent_app_number] => 17/195824 [patent_app_country] => US [patent_app_date] => 2021-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11172 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17195824 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/195824
Non-volatile memory device and an operation method thereof Mar 8, 2021 Issued
Array ( [id] => 17447884 [patent_doc_number] => 20220068389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/191563 [patent_app_country] => US [patent_app_date] => 2021-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7900 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17191563 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/191563
Semiconductor storage device Mar 2, 2021 Issued
Array ( [id] => 18174969 [patent_doc_number] => 11574686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 17/190638 [patent_app_country] => US [patent_app_date] => 2021-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 48 [patent_no_of_words] => 24495 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17190638 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/190638
Memory system Mar 2, 2021 Issued
Array ( [id] => 17447883 [patent_doc_number] => 20220068388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/191530 [patent_app_country] => US [patent_app_date] => 2021-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12918 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17191530 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/191530
Memory device and operating method thereof Mar 2, 2021 Issued
Array ( [id] => 18719695 [patent_doc_number] => 11797037 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Voltage regulation for multiple voltage levels [patent_app_type] => utility [patent_app_number] => 17/186511 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6179 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17186511 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/186511
Voltage regulation for multiple voltage levels Feb 25, 2021 Issued
Array ( [id] => 17070417 [patent_doc_number] => 20210272634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND READING METHOD [patent_app_type] => utility [patent_app_number] => 17/179409 [patent_app_country] => US [patent_app_date] => 2021-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5054 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17179409 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/179409
Semiconductor memory device and reading method Feb 18, 2021 Issued
Array ( [id] => 16918723 [patent_doc_number] => 20210191815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => READ DISTURB SCAN CONSOLIDATION [patent_app_type] => utility [patent_app_number] => 17/249087 [patent_app_country] => US [patent_app_date] => 2021-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11414 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17249087 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/249087
Read disturb scan consolidation Feb 18, 2021 Issued
Array ( [id] => 17745454 [patent_doc_number] => 11393533 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-07-19 [patent_title] => Estimating resistance-capacitance time constant of electrical circuit [patent_app_type] => utility [patent_app_number] => 17/175301 [patent_app_country] => US [patent_app_date] => 2021-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7265 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17175301 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/175301
Estimating resistance-capacitance time constant of electrical circuit Feb 11, 2021 Issued
Array ( [id] => 17040386 [patent_doc_number] => 20210257022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => AUTO-REFERENCED MEMORY CELL READ TECHNIQUES [patent_app_type] => utility [patent_app_number] => 17/165579 [patent_app_country] => US [patent_app_date] => 2021-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20023 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17165579 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/165579
Auto-referenced memory cell read techniques Feb 1, 2021 Issued
Array ( [id] => 17699978 [patent_doc_number] => 11373710 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-06-28 [patent_title] => Time division peak power management for non-volatile storage [patent_app_type] => utility [patent_app_number] => 17/165703 [patent_app_country] => US [patent_app_date] => 2021-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 29 [patent_no_of_words] => 16550 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17165703 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/165703
Time division peak power management for non-volatile storage Feb 1, 2021 Issued
Array ( [id] => 17416835 [patent_doc_number] => 20220051739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/161295 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14610 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17161295 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/161295
Memory device and method of operating the same Jan 27, 2021 Issued
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