Search

Jason Lappas

Examiner (ID: 1768, Phone: (571)270-1272 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
1429
Issued Applications
1309
Pending Applications
77
Abandoned Applications
64

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19773132 [patent_doc_number] => 20250054558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => ONE-TIME PROGRAMMABLE MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/932800 [patent_app_country] => US [patent_app_date] => 2024-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14082 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18932800 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/932800
ONE-TIME PROGRAMMABLE MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME Oct 30, 2024 Pending
Array ( [id] => 20028496 [patent_doc_number] => 20250166718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => DETECTING EXTRINSIC BITLINE DEFECTS [patent_app_type] => utility [patent_app_number] => 18/932023 [patent_app_country] => US [patent_app_date] => 2024-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4688 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18932023 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/932023
DETECTING EXTRINSIC BITLINE DEFECTS Oct 29, 2024 Pending
Array ( [id] => 20681912 [patent_doc_number] => 20260120737 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-30 [patent_title] => BREAKDOWN MITIGATION FOR PROGRAMMABLE RESISTANCE MEMORY ELEMENT [patent_app_type] => utility [patent_app_number] => 18/931452 [patent_app_country] => US [patent_app_date] => 2024-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16410 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18931452 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/931452
BREAKDOWN MITIGATION FOR PROGRAMMABLE RESISTANCE MEMORY ELEMENT Oct 29, 2024 Pending
Array ( [id] => 20601615 [patent_doc_number] => 20260079624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-19 [patent_title] => SYSTEMS AND METHODS FOR HIGH PERFORMANCE READ WITH ROW-TO-ROW THRESHOLD TRACKING IN NVM [patent_app_type] => utility [patent_app_number] => 18/921462 [patent_app_country] => US [patent_app_date] => 2024-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8055 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18921462 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/921462
SYSTEMS AND METHODS FOR HIGH PERFORMANCE READ WITH ROW-TO-ROW THRESHOLD TRACKING IN NVM Oct 20, 2024 Pending
Array ( [id] => 20660346 [patent_doc_number] => 20260112397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-23 [patent_title] => CLOCK LEVELING FOR MEMORY INTERFACES [patent_app_type] => utility [patent_app_number] => 18/919598 [patent_app_country] => US [patent_app_date] => 2024-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6038 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18919598 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/919598
CLOCK LEVELING FOR MEMORY INTERFACES Oct 17, 2024 Pending
Array ( [id] => 20002079 [patent_doc_number] => 20250140301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => CONTROL MODULE AND CONTROL METHOD THEREOF FOR SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 18/919186 [patent_app_country] => US [patent_app_date] => 2024-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18919186 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/919186
CONTROL MODULE AND CONTROL METHOD THEREOF FOR SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY Oct 16, 2024 Pending
Array ( [id] => 20884406 [patent_doc_number] => 12700450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-04 [patent_title] => Offset compensated sense amplifier and memory devices including the same [patent_app_type] => utility [patent_app_number] => 18/905764 [patent_app_country] => US [patent_app_date] => 2024-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 7042 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18905764 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/905764
OFFSET COMPENSATED SENSE AMPLIFIER AND MEMORY DEVICES INCLUDING THE SAME Oct 2, 2024 Pending
Array ( [id] => 19894750 [patent_doc_number] => 20250120062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => MEMORY DEVICE USING SEMICONDUCTOR ELEMENT [patent_app_type] => utility [patent_app_number] => 18/900034 [patent_app_country] => US [patent_app_date] => 2024-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7848 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 597 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18900034 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/900034
Memory device using semiconductor element Sep 26, 2024 Issued
Array ( [id] => 20004607 [patent_doc_number] => 20250142829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/897719 [patent_app_country] => US [patent_app_date] => 2024-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11358 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18897719 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/897719
THREE-DIMENSIONAL MEMORY DEVICE Sep 25, 2024 Pending
Array ( [id] => 20088562 [patent_doc_number] => 20250218498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => SENSE AMPLIFIER AND METHOD OF OPERATION THEREOF [patent_app_type] => utility [patent_app_number] => 18/887289 [patent_app_country] => US [patent_app_date] => 2024-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6961 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18887289 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/887289
Sense amplifier and method of operation thereof Sep 16, 2024 Issued
Array ( [id] => 19687711 [patent_doc_number] => 20250006256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/886279 [patent_app_country] => US [patent_app_date] => 2024-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9110 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18886279 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/886279
MEMORY DEVICE AND METHOD OF OPERATING THE SAME Sep 15, 2024 Pending
Array ( [id] => 20019331 [patent_doc_number] => 20250157553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => MEMORY DEVICE AND METHOD FOR CONTROLLING VERIFICATION VOLTAGE OF MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/882728 [patent_app_country] => US [patent_app_date] => 2024-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18882728 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/882728
Memory device and method for controlling verification voltage of memory device Sep 10, 2024 Issued
Array ( [id] => 19661779 [patent_doc_number] => 20240428844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => APPARATUSES, SYSTEMS, AND METHODS FOR DATA TIMING ALIGNMENT WITH FAST ALIGNMENT MODE [patent_app_type] => utility [patent_app_number] => 18/830393 [patent_app_country] => US [patent_app_date] => 2024-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13402 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18830393 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/830393
APPARATUSES, SYSTEMS, AND METHODS FOR DATA TIMING ALIGNMENT WITH FAST ALIGNMENT MODE Sep 9, 2024 Pending
Array ( [id] => 19687705 [patent_doc_number] => 20250006250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => TECHNIQUES TO COUPLE HIGH BANDWIDTH MEMORY DEVICE ON SILICON SUBSTRATE AND PACKAGE SUBSTRATE [patent_app_type] => utility [patent_app_number] => 18/828845 [patent_app_country] => US [patent_app_date] => 2024-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9869 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18828845 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/828845
TECHNIQUES TO COUPLE HIGH BANDWIDTH MEMORY DEVICE ON SILICON SUBSTRATE AND PACKAGE SUBSTRATE Sep 8, 2024 Pending
Array ( [id] => 19661776 [patent_doc_number] => 20240428841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => APPARATUSES AND METHODS FOR PARTIAL ARRAY SELF REFRESH MASKING [patent_app_type] => utility [patent_app_number] => 18/824515 [patent_app_country] => US [patent_app_date] => 2024-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8704 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18824515 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/824515
Apparatuses and methods for partial array self refresh masking Sep 3, 2024 Issued
Array ( [id] => 20820697 [patent_doc_number] => 12676170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-07 [patent_title] => Bitline sense amplifiers and semiconductor devices including the same [patent_app_type] => utility [patent_app_number] => 18/822985 [patent_app_country] => US [patent_app_date] => 2024-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 5779 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18822985 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/822985
Bitline sense amplifiers and semiconductor devices including the same Sep 2, 2024 Issued
Array ( [id] => 19835463 [patent_doc_number] => 20250087249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => INTERCONNECTIONS FOR 3D MEMORY [patent_app_type] => utility [patent_app_number] => 18/811059 [patent_app_country] => US [patent_app_date] => 2024-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7409 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18811059 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/811059
INTERCONNECTIONS FOR 3D MEMORY Aug 20, 2024 Pending
Array ( [id] => 19773135 [patent_doc_number] => 20250054561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => TIMING-DRIFT CALIBRATION [patent_app_type] => utility [patent_app_number] => 18/809250 [patent_app_country] => US [patent_app_date] => 2024-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4876 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18809250 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/809250
TIMING-DRIFT CALIBRATION Aug 18, 2024 Pending
Array ( [id] => 19604451 [patent_doc_number] => 20240395331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => ARCHITECTURE AND METHOD FOR NAND MEMORY OPERATION [patent_app_type] => utility [patent_app_number] => 18/798320 [patent_app_country] => US [patent_app_date] => 2024-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7344 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18798320 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/798320
ARCHITECTURE AND METHOD FOR NAND MEMORY OPERATION Aug 7, 2024 Pending
Array ( [id] => 19604440 [patent_doc_number] => 20240395320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => MEMORY WITH DOUBLE REDUNDANCY [patent_app_type] => utility [patent_app_number] => 18/796143 [patent_app_country] => US [patent_app_date] => 2024-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10439 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18796143 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/796143
Memory with double redundancy Aug 5, 2024 Issued
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