Search

Jason Lappas

Examiner (ID: 3968, Phone: (571)270-1272 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
1390
Issued Applications
1293
Pending Applications
55
Abandoned Applications
64

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16193890 [patent_doc_number] => 20200234739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => LOW VOLTAGE DETECTION CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/843702 [patent_app_country] => US [patent_app_date] => 2020-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13025 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16843702 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/843702
Low voltage detection circuit and memory device including the same Apr 7, 2020 Issued
Array ( [id] => 16926960 [patent_doc_number] => 11048443 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-06-29 [patent_title] => Non-volatile memory interface [patent_app_type] => utility [patent_app_number] => 16/830128 [patent_app_country] => US [patent_app_date] => 2020-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13755 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16830128 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/830128
Non-volatile memory interface Mar 24, 2020 Issued
Array ( [id] => 16034513 [patent_doc_number] => 10679683 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-06-09 [patent_title] => Timing circuit for command path in a memory device [patent_app_type] => utility [patent_app_number] => 16/825096 [patent_app_country] => US [patent_app_date] => 2020-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6892 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16825096 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/825096
Timing circuit for command path in a memory device Mar 19, 2020 Issued
Array ( [id] => 16347771 [patent_doc_number] => 20200312422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => TIMING-DRIFT CALIBRATION [patent_app_type] => utility [patent_app_number] => 16/824005 [patent_app_country] => US [patent_app_date] => 2020-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4841 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16824005 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/824005
Timing-drift calibration Mar 18, 2020 Issued
Array ( [id] => 16879743 [patent_doc_number] => 11029890 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-06-08 [patent_title] => Compound feature generation in classification of error rate of data retrieved from memory cells [patent_app_type] => utility [patent_app_number] => 16/807063 [patent_app_country] => US [patent_app_date] => 2020-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 12403 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16807063 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/807063
Compound feature generation in classification of error rate of data retrieved from memory cells Mar 1, 2020 Issued
Array ( [id] => 17070422 [patent_doc_number] => 20210272639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => DETECTION OF A LAST PROGRAMMING LOOP FOR SYSTEM PERFORMANCE GAIN [patent_app_type] => utility [patent_app_number] => 16/803366 [patent_app_country] => US [patent_app_date] => 2020-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14148 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16803366 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/803366
Detection of a last programming loop for system performance gain Feb 26, 2020 Issued
Array ( [id] => 17691839 [patent_doc_number] => 20220199132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => LOW POWER MEMORY WITH ON-DEMAND BANDWIDTH BOOST [patent_app_type] => utility [patent_app_number] => 17/432064 [patent_app_country] => US [patent_app_date] => 2020-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8620 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17432064 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/432064
Low power memory with on-demand bandwidth boost Feb 24, 2020 Issued
Array ( [id] => 17239342 [patent_doc_number] => 11183230 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Sense amplifier circuit and semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/799196 [patent_app_country] => US [patent_app_date] => 2020-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10848 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16799196 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/799196
Sense amplifier circuit and semiconductor memory device Feb 23, 2020 Issued
Array ( [id] => 17224497 [patent_doc_number] => 11177007 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Feedback for power management of a memory die using capacitive coupling [patent_app_type] => utility [patent_app_number] => 16/798893 [patent_app_country] => US [patent_app_date] => 2020-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10842 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16798893 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/798893
Feedback for power management of a memory die using capacitive coupling Feb 23, 2020 Issued
Array ( [id] => 19062922 [patent_doc_number] => 11942167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Fuse array layout pattern and related apparatuses, systems, and methods [patent_app_type] => utility [patent_app_number] => 16/799011 [patent_app_country] => US [patent_app_date] => 2020-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6436 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16799011 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/799011
Fuse array layout pattern and related apparatuses, systems, and methods Feb 23, 2020 Issued
Array ( [id] => 17055530 [patent_doc_number] => 20210264964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => SOURCE SIDE PRECHARGE AND BOOSTING IMPROVEMENT FOR REVERSE ORDER PROGRAM [patent_app_type] => utility [patent_app_number] => 16/798718 [patent_app_country] => US [patent_app_date] => 2020-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16798718 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/798718
Source side precharge and boosting improvement for reverse order program Feb 23, 2020 Issued
Array ( [id] => 16623399 [patent_doc_number] => 20210042052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 16/799360 [patent_app_country] => US [patent_app_date] => 2020-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8020 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16799360 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/799360
Storage device Feb 23, 2020 Issued
Array ( [id] => 16746215 [patent_doc_number] => 10971215 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-06 [patent_title] => Dynamically adjust data transfer speed for non-volatile memory die interfaces [patent_app_type] => utility [patent_app_number] => 16/798590 [patent_app_country] => US [patent_app_date] => 2020-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13879 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16798590 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/798590
Dynamically adjust data transfer speed for non-volatile memory die interfaces Feb 23, 2020 Issued
Array ( [id] => 16845775 [patent_doc_number] => 11017870 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-05-25 [patent_title] => Select gate maintenance in a memory sub-system [patent_app_type] => utility [patent_app_number] => 16/798832 [patent_app_country] => US [patent_app_date] => 2020-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8676 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16798832 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/798832
Select gate maintenance in a memory sub-system Feb 23, 2020 Issued
Array ( [id] => 16255600 [patent_doc_number] => 20200264974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => DECODING OF HIGH-DENSITY MEMORY CELLS IN A SOLID-STATE DRIVE [patent_app_type] => utility [patent_app_number] => 16/796378 [patent_app_country] => US [patent_app_date] => 2020-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4382 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16796378 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/796378
Decoding of high-density memory cells in a solid-state drive Feb 19, 2020 Issued
Array ( [id] => 16172578 [patent_doc_number] => 10714154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => Semiconductor integrated circuit device and semiconductor device [patent_app_type] => utility [patent_app_number] => 16/794907 [patent_app_country] => US [patent_app_date] => 2020-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 7638 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16794907 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/794907
Semiconductor integrated circuit device and semiconductor device Feb 18, 2020 Issued
Array ( [id] => 16315848 [patent_doc_number] => 20200294586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => AUTO-REFERENCED MEMORY CELL READ TECHNIQUES [patent_app_type] => utility [patent_app_number] => 16/791764 [patent_app_country] => US [patent_app_date] => 2020-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20677 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16791764 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/791764
Auto-referenced memory cell read techniques Feb 13, 2020 Issued
Array ( [id] => 16000399 [patent_doc_number] => 20200176070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => METHODS AND APPARATUSES FOR SELF-TRIMMING OF A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/784046 [patent_app_country] => US [patent_app_date] => 2020-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16784046 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/784046
Methods and apparatuses for self-trimming of a semiconductor device Feb 5, 2020 Issued
Array ( [id] => 16645329 [patent_doc_number] => 10923193 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-16 [patent_title] => Memory device including voltage generating circuit [patent_app_type] => utility [patent_app_number] => 16/749657 [patent_app_country] => US [patent_app_date] => 2020-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 7268 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16749657 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/749657
Memory device including voltage generating circuit Jan 21, 2020 Issued
Array ( [id] => 16299671 [patent_doc_number] => 20200285394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => FLIP-FLOP BASED ON NONVOLATILE MEMORY AND BACKUP OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/747875 [patent_app_country] => US [patent_app_date] => 2020-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7040 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16747875 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/747875
Flip-flop based on nonvolatile memory and backup operation method thereof Jan 20, 2020 Issued
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