Search

Jason Lappas

Examiner (ID: 3968, Phone: (571)270-1272 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
1390
Issued Applications
1293
Pending Applications
55
Abandoned Applications
64

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14285779 [patent_doc_number] => 20190140174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => METHODS, APPARATUSES, AND CIRCUITS FOR PROGRAMMING A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/184314 [patent_app_country] => US [patent_app_date] => 2018-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5610 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16184314 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/184314
Methods, apparatuses, and circuits for programming a memory device Nov 7, 2018 Issued
Array ( [id] => 15331009 [patent_doc_number] => 20200005834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => LATCH-UP PREVENTION CIRCUIT FOR MEMORY STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 16/179332 [patent_app_country] => US [patent_app_date] => 2018-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7861 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16179332 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/179332
Latch-up prevention circuit for memory storage system Nov 1, 2018 Issued
Array ( [id] => 15122901 [patent_doc_number] => 20190348084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/179046 [patent_app_country] => US [patent_app_date] => 2018-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15927 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -33 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16179046 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/179046
Semiconductor devices Nov 1, 2018 Issued
Array ( [id] => 15872949 [patent_doc_number] => 20200143878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => RESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD FOR PERFORMING MEMORY OPERATIONS [patent_app_type] => utility [patent_app_number] => 16/178602 [patent_app_country] => US [patent_app_date] => 2018-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3757 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16178602 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/178602
Resistive random access memory device and method for performing memory operations Nov 1, 2018 Issued
Array ( [id] => 15872899 [patent_doc_number] => 20200143853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => DATA AND CLOCK SYNCHRONIZATION AND VARIATION COMPENSATION APPARATUS AND METHOD [patent_app_type] => utility [patent_app_number] => 16/178346 [patent_app_country] => US [patent_app_date] => 2018-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7761 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16178346 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/178346
Data and clock synchronization and variation compensation apparatus and method Oct 31, 2018 Issued
Array ( [id] => 16432659 [patent_doc_number] => 10832751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Magnetic memory and method for using the same [patent_app_type] => utility [patent_app_number] => 16/176292 [patent_app_country] => US [patent_app_date] => 2018-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6177 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16176292 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/176292
Magnetic memory and method for using the same Oct 30, 2018 Issued
Array ( [id] => 15839963 [patent_doc_number] => 20200135264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => PERFORMING AN ON DEMAND REFRESH OPERATION OF A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 16/177216 [patent_app_country] => US [patent_app_date] => 2018-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10033 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16177216 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/177216
Performing an on demand refresh operation of a memory sub-system Oct 30, 2018 Issued
Array ( [id] => 15839961 [patent_doc_number] => 20200135263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => APPARATUSES AND METHODS FOR ACCESS BASED REFRESH TIMING [patent_app_type] => utility [patent_app_number] => 16/176932 [patent_app_country] => US [patent_app_date] => 2018-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9412 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16176932 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/176932
Apparatuses and methods for access based refresh timing Oct 30, 2018 Issued
Array ( [id] => 15249723 [patent_doc_number] => 10510388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-17 [patent_title] => On-die termination of address and command signals [patent_app_type] => utility [patent_app_number] => 16/174180 [patent_app_country] => US [patent_app_date] => 2018-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3641 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16174180 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/174180
On-die termination of address and command signals Oct 28, 2018 Issued
Array ( [id] => 15889033 [patent_doc_number] => 10650865 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Low voltage detection circuit and memory device including the same [patent_app_type] => utility [patent_app_number] => 16/170934 [patent_app_country] => US [patent_app_date] => 2018-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 13010 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16170934 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/170934
Low voltage detection circuit and memory device including the same Oct 24, 2018 Issued
Array ( [id] => 14237585 [patent_doc_number] => 20190130965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => Mitigating Write Disturbance in Dual Port 8T SRAM [patent_app_type] => utility [patent_app_number] => 16/171246 [patent_app_country] => US [patent_app_date] => 2018-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14047 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16171246 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/171246
Mitigating write disturbance in dual port 8T SRAM Oct 24, 2018 Issued
Array ( [id] => 17470337 [patent_doc_number] => 11276820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-15 [patent_title] => Memristor and neural network using same [patent_app_type] => utility [patent_app_number] => 16/756993 [patent_app_country] => US [patent_app_date] => 2018-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3991 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16756993 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/756993
Memristor and neural network using same Oct 18, 2018 Issued
Array ( [id] => 13861825 [patent_doc_number] => 10192635 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-01-29 [patent_title] => FinFET-based memory testing using multiple read operations [patent_app_type] => utility [patent_app_number] => 16/147377 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 6581 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147377 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/147377
FinFET-based memory testing using multiple read operations Sep 27, 2018 Issued
Array ( [id] => 14768681 [patent_doc_number] => 10395741 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Nonvolatile memory device [patent_app_type] => utility [patent_app_number] => 16/139921 [patent_app_country] => US [patent_app_date] => 2018-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8791 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16139921 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/139921
Nonvolatile memory device Sep 23, 2018 Issued
Array ( [id] => 13847419 [patent_doc_number] => 20190027194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => INTERCONNECTIONS FOR 3D MEMORY [patent_app_type] => utility [patent_app_number] => 16/137309 [patent_app_country] => US [patent_app_date] => 2018-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7297 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16137309 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/137309
Interconnections for 3D memory Sep 19, 2018 Issued
Array ( [id] => 14267261 [patent_doc_number] => 10283200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => Impedance tuning between packaging and dies [patent_app_type] => utility [patent_app_number] => 16/126826 [patent_app_country] => US [patent_app_date] => 2018-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 10704 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16126826 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/126826
Impedance tuning between packaging and dies Sep 9, 2018 Issued
Array ( [id] => 13808145 [patent_doc_number] => 10181341 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-01-15 [patent_title] => Memory device including current generator plate [patent_app_type] => utility [patent_app_number] => 16/125315 [patent_app_country] => US [patent_app_date] => 2018-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 26 [patent_no_of_words] => 14975 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16125315 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/125315
Memory device including current generator plate Sep 6, 2018 Issued
Array ( [id] => 13962811 [patent_doc_number] => 20190057750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-21 [patent_title] => METHODS AND OPERATIONS USING XNOR FUNCTIONS WITH FLASH DEVICES AND SOLID STATE DRIVES [patent_app_type] => utility [patent_app_number] => 16/104696 [patent_app_country] => US [patent_app_date] => 2018-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5245 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16104696 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/104696
Methods and operations using XNOR functions with flash devices and solid state drives Aug 16, 2018 Issued
Array ( [id] => 15532093 [patent_doc_number] => 20200058352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-20 [patent_title] => Crossbar array with reduced disturbance [patent_app_type] => utility [patent_app_number] => 15/999140 [patent_app_country] => US [patent_app_date] => 2018-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5412 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15999140 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/999140
Crossbar array with reduced disturbance Aug 16, 2018 Issued
Array ( [id] => 15286035 [patent_doc_number] => 10515686 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-24 [patent_title] => Low voltage reference current generator and memory device using same [patent_app_type] => utility [patent_app_number] => 16/054586 [patent_app_country] => US [patent_app_date] => 2018-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3131 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16054586 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/054586
Low voltage reference current generator and memory device using same Aug 2, 2018 Issued
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