Jason Lappas

Array ( [id] => 19604449 [patent_doc_number] => 20240395329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => PADDING IN FLASH MEMORY BLOCKS [patent_app_type] => utility [patent_app_number] => 18/793392 [patent_app_country] => US [patent_app_date] => 2024-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8410 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18793392 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20774551 [patent_doc_number] => 12658230 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-16 [patent_title] => Memory device, method of operating the memory device, and memory system [patent_app_type] => utility [patent_app_number] => 18/791722 [patent_app_country] => US [patent_app_date] => 2024-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 4834 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18791722 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20291067 [patent_doc_number] => 20250316310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => MEMORY CELL [patent_app_type] => utility [patent_app_number] => 18/791999 [patent_app_country] => US [patent_app_date] => 2024-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3248 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18791999 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19893074 [patent_doc_number] => 20250118386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => SEMICONDUCTOR MEMORY DEVICE WITH PROCESSING-IN-MEMORY USING TEST CIRCUITRY [patent_app_type] => utility [patent_app_number] => 18/789680 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8125 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18789680 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19803707 [patent_doc_number] => 20250069632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => CRITICAL TIMING DRIVEN ADAPTIVE VOLTAGE FREQUENCY SCALING [patent_app_type] => utility [patent_app_number] => 18/787812 [patent_app_country] => US [patent_app_date] => 2024-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14310 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18787812 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19850367 [patent_doc_number] => 20250095718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => CAPACITANCE BALANCING IN SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/788001 [patent_app_country] => US [patent_app_date] => 2024-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10312 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18788001 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19589408 [patent_doc_number] => 20240386965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => USING NON-SEGREGATED CELLS AS DRAIN-SIDE SELECT GATES FOR SUB-BLOCKS IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/787957 [patent_app_country] => US [patent_app_date] => 2024-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18787957 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19589372 [patent_doc_number] => 20240386929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => ADJUSTABLE DELAY PROPAGATION OF A CONTROL SIGNAL TO DIFFERENT PAGE BUFFER DRIVER GROUPS [patent_app_type] => utility [patent_app_number] => 18/786234 [patent_app_country] => US [patent_app_date] => 2024-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13594 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18786234 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20883625 [patent_doc_number] => 12699668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-04 [patent_title] => Systems and methods of testing memory devices [patent_app_type] => utility [patent_app_number] => 18/783126 [patent_app_country] => US [patent_app_date] => 2024-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 10028 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18783126 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19574884 [patent_doc_number] => 20240379176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => PARTIAL BLOCK ERASE OPERATIONS IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/781317 [patent_app_country] => US [patent_app_date] => 2024-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9209 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18781317 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20235535 [patent_doc_number] => 20250292854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/771019 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4660 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771019 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20776912 [patent_doc_number] => 12660610 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-16 [patent_title] => Electrical fuse bit cell in integrated circuit having backside conducting lines [patent_app_type] => utility [patent_app_number] => 18/771536 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 35 [patent_no_of_words] => 8692 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771536 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20311760 [patent_doc_number] => 20250329389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => MANAGING PROGRAM DISTURB IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/770632 [patent_app_country] => US [patent_app_date] => 2024-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18770632 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19712380 [patent_doc_number] => 20250022522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => ELECTROCHEMICAL CHARGE STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/768870 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9480 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18768870 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19835489 [patent_doc_number] => 20250087275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => SELECTIVELY ERASING ONE OF MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING USING GATE INDUCED DRAIN LEAKAGE [patent_app_type] => utility [patent_app_number] => 18/768970 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9629 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18768970 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20482647 [patent_doc_number] => 12531123 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Non-volatile memory with auxiliary select gate line driver [patent_app_type] => utility [patent_app_number] => 18/765358 [patent_app_country] => US [patent_app_date] => 2024-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 40 [patent_no_of_words] => 4420 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 450 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18765358 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19934862 [patent_doc_number] => 12308070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Word line drivers for multiple-die memory devices [patent_app_type] => utility [patent_app_number] => 18/765076 [patent_app_country] => US [patent_app_date] => 2024-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 14028 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18765076 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19515398 [patent_doc_number] => 20240347084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => DETERMINING READ VOLTAGE OFFSET IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/755033 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10079 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18755033 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19951084 [patent_doc_number] => 12322454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Nonvolatile semiconductor memory device including a memory cell array and a control circuit applying a reading voltage [patent_app_type] => utility [patent_app_number] => 18/752870 [patent_app_country] => US [patent_app_date] => 2024-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 31 [patent_no_of_words] => 6320 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18752870 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19687722 [patent_doc_number] => 20250006267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => NON-VOLATILE MEMORY AND CORRESPONDING MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 18/753094 [patent_app_country] => US [patent_app_date] => 2024-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7595 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18753094 [rel_patent_id] =>[rel_patent_doc_number] =>)