Search

Jason Lappas

Examiner (ID: 3968, Phone: (571)270-1272 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
1390
Issued Applications
1293
Pending Applications
55
Abandoned Applications
64

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12435738 [patent_doc_number] => 09978428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-22 [patent_title] => Semiconductor device and power distribution network [patent_app_type] => utility [patent_app_number] => 15/485344 [patent_app_country] => US [patent_app_date] => 2017-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3762 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15485344 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/485344
Semiconductor device and power distribution network Apr 11, 2017 Issued
Array ( [id] => 12095307 [patent_doc_number] => 20170352400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND REFRESH METHOD OF SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/484244 [patent_app_country] => US [patent_app_date] => 2017-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4768 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15484244 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/484244
Semiconductor memory device and refresh method of semiconductor memory device Apr 10, 2017 Issued
Array ( [id] => 12758896 [patent_doc_number] => 20180144800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/484580 [patent_app_country] => US [patent_app_date] => 2017-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8781 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15484580 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/484580
Nonvolatile memory device Apr 10, 2017 Issued
Array ( [id] => 13976289 [patent_doc_number] => 10217508 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-26 [patent_title] => SRAM and periphery specialized device sensors [patent_app_type] => utility [patent_app_number] => 15/485220 [patent_app_country] => US [patent_app_date] => 2017-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4636 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15485220 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/485220
SRAM and periphery specialized device sensors Apr 10, 2017 Issued
Array ( [id] => 13003693 [patent_doc_number] => 10025514 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => Memory system and method of controlling nonvolatile memory [patent_app_type] => utility [patent_app_number] => 15/481553 [patent_app_country] => US [patent_app_date] => 2017-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 9176 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15481553 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/481553
Memory system and method of controlling nonvolatile memory Apr 6, 2017 Issued
Array ( [id] => 11918143 [patent_doc_number] => 09786333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-10 [patent_title] => 'Dual-bit 3-T high density MTPROM array' [patent_app_type] => utility [patent_app_number] => 15/478820 [patent_app_country] => US [patent_app_date] => 2017-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6432 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15478820 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/478820
Dual-bit 3-T high density MTPROM array Apr 3, 2017 Issued
Array ( [id] => 11760360 [patent_doc_number] => 20170207229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-20 [patent_title] => 'VOLTAGE SWITCHING CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/477612 [patent_app_country] => US [patent_app_date] => 2017-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4487 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15477612 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/477612
Voltage switching circuit and semiconductor apparatus including the same Apr 2, 2017 Issued
Array ( [id] => 12497892 [patent_doc_number] => 09997253 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-06-12 [patent_title] => Non-volatile memory array with memory gate line and source line scrambling [patent_app_type] => utility [patent_app_number] => 15/471418 [patent_app_country] => US [patent_app_date] => 2017-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 8969 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15471418 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/471418
Non-volatile memory array with memory gate line and source line scrambling Mar 27, 2017 Issued
Array ( [id] => 12088909 [patent_doc_number] => 09842641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-12 [patent_title] => 'Semiconductor device and operating method thereof' [patent_app_type] => utility [patent_app_number] => 15/470593 [patent_app_country] => US [patent_app_date] => 2017-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3133 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15470593 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/470593
Semiconductor device and operating method thereof Mar 26, 2017 Issued
Array ( [id] => 13201047 [patent_doc_number] => 10115443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-30 [patent_title] => Techniques to improve switching probability and switching speed in SOT devices [patent_app_type] => utility [patent_app_number] => 15/458196 [patent_app_country] => US [patent_app_date] => 2017-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 5309 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15458196 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/458196
Techniques to improve switching probability and switching speed in SOT devices Mar 13, 2017 Issued
Array ( [id] => 11966872 [patent_doc_number] => 20170271025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'SEMICONDUCTOR STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 15/455970 [patent_app_country] => US [patent_app_date] => 2017-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 12822 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15455970 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/455970
Semiconductor storage device Mar 9, 2017 Issued
Array ( [id] => 12573348 [patent_doc_number] => 10020040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-10 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 15/455906 [patent_app_country] => US [patent_app_date] => 2017-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 15171 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15455906 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/455906
Semiconductor memory device Mar 9, 2017 Issued
Array ( [id] => 13111531 [patent_doc_number] => 10074423 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-09-11 [patent_title] => Impedance tuning between packaging and dies [patent_app_type] => utility [patent_app_number] => 15/453418 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 10656 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15453418 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/453418
Impedance tuning between packaging and dies Mar 7, 2017 Issued
Array ( [id] => 12181423 [patent_doc_number] => 20180040358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'NONVOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 15/453626 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 53 [patent_no_of_words] => 25401 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15453626 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/453626
NONVOLATILE MEMORY Mar 7, 2017 Abandoned
Array ( [id] => 13005615 [patent_doc_number] => 10026478 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-17 [patent_title] => Biasing scheme for multi-layer cross-point ReRAM [patent_app_type] => utility [patent_app_number] => 15/448602 [patent_app_country] => US [patent_app_date] => 2017-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 14626 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15448602 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/448602
Biasing scheme for multi-layer cross-point ReRAM Mar 2, 2017 Issued
Array ( [id] => 12229645 [patent_doc_number] => 09916892 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-13 [patent_title] => 'Write driver circuitry to reduce leakage of negative boost charge' [patent_app_type] => utility [patent_app_number] => 15/448526 [patent_app_country] => US [patent_app_date] => 2017-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3842 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15448526 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/448526
Write driver circuitry to reduce leakage of negative boost charge Mar 1, 2017 Issued
Array ( [id] => 11694171 [patent_doc_number] => 20170169889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/444274 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 14298 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15444274 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/444274
Semiconductor memory device Feb 26, 2017 Issued
Array ( [id] => 11694147 [patent_doc_number] => 20170169864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'MEMORY ARRAY AND METHOD OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/443418 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5747 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15443418 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/443418
Memory array and method of forming the same Feb 26, 2017 Issued
Array ( [id] => 13377969 [patent_doc_number] => 20180240526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-23 [patent_title] => DYNAMIC STROBE TIMING [patent_app_type] => utility [patent_app_number] => 15/440940 [patent_app_country] => US [patent_app_date] => 2017-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11763 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15440940 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/440940
Dynamic strobe timing Feb 22, 2017 Issued
Array ( [id] => 11855152 [patent_doc_number] => 20170229644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-10 [patent_title] => 'METHODS, APPARATUSES, AND CIRCUITS FOR PROGRAMMING A MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/438499 [patent_app_country] => US [patent_app_date] => 2017-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5661 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15438499 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/438499
Methods, apparatuses, and circuits for programming a memory device Feb 20, 2017 Issued
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