
Jason Lappas
Examiner (ID: 1768, Phone: (571)270-1272 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2827 |
| Total Applications | 1429 |
| Issued Applications | 1309 |
| Pending Applications | 77 |
| Abandoned Applications | 64 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20690284
[patent_doc_number] => 12620441
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-05-05
[patent_title] => Memory, operation method of memory, and memory system
[patent_app_type] => utility
[patent_app_number] => 18/750641
[patent_app_country] => US
[patent_app_date] => 2024-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 20
[patent_no_of_words] => 9413
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 234
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18750641
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/750641 | Memory, operation method of memory, and memory system | Jun 20, 2024 | Issued |
Array
(
[id] => 19788251
[patent_doc_number] => 20250061930
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-02-20
[patent_title] => Truncated Resolution for Time Sliced Computation of Multiplication and Accumulation using a Memory Cell Array
[patent_app_type] => utility
[patent_app_number] => 18/751094
[patent_app_country] => US
[patent_app_date] => 2024-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12248
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18751094
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/751094 | Truncated Resolution for Time Sliced Computation of Multiplication and Accumulation using a Memory Cell Array | Jun 20, 2024 | Pending |
Array
(
[id] => 20422850
[patent_doc_number] => 20250384935
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-12-18
[patent_title] => MEMORY DEVICE AND DATA ACCESSING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/741780
[patent_app_country] => US
[patent_app_date] => 2024-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18741780
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/741780 | Memory device and data accessing method thereof | Jun 12, 2024 | Issued |
Array
(
[id] => 19749181
[patent_doc_number] => 20250037746
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-30
[patent_title] => On-Die Termination of Address and Command Signals
[patent_app_type] => utility
[patent_app_number] => 18/680395
[patent_app_country] => US
[patent_app_date] => 2024-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3755
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18680395
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/680395 | On-die termination of address and command signals | May 30, 2024 | Issued |
Array
(
[id] => 19452403
[patent_doc_number] => 20240312533
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-19
[patent_title] => MEMORY SYSTEM, CONTROL METHOD THEREOF, AND PROGRAM
[patent_app_type] => utility
[patent_app_number] => 18/677727
[patent_app_country] => US
[patent_app_date] => 2024-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13651
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18677727
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/677727 | Memory system, control method thereof, and program | May 28, 2024 | Issued |
Array
(
[id] => 19926022
[patent_doc_number] => 12300314
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-13
[patent_title] => Memory system and memory device
[patent_app_type] => utility
[patent_app_number] => 18/675257
[patent_app_country] => US
[patent_app_date] => 2024-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 68
[patent_figures_cnt] => 75
[patent_no_of_words] => 38695
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 209
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675257
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/675257 | Memory system and memory device | May 27, 2024 | Issued |
Array
(
[id] => 20297635
[patent_doc_number] => 20250322878
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-10-16
[patent_title] => MEMORY DEVICE, MEMORY SYSTEM, AND METHOD OF OPERATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/676135
[patent_app_country] => US
[patent_app_date] => 2024-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2524
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18676135
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/676135 | MEMORY DEVICE, MEMORY SYSTEM, AND METHOD OF OPERATING THE SAME | May 27, 2024 | Pending |
Array
(
[id] => 20434900
[patent_doc_number] => 12505887
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-23
[patent_title] => Discharge circuits for a NAND flash memory
[patent_app_type] => utility
[patent_app_number] => 18/663879
[patent_app_country] => US
[patent_app_date] => 2024-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 16
[patent_no_of_words] => 5820
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663879
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/663879 | Discharge circuits for a NAND flash memory | May 13, 2024 | Issued |
Array
(
[id] => 19589406
[patent_doc_number] => 20240386963
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-21
[patent_title] => PROGRAMMING TECHNIQUES FOR POLARITY-BASED MEMORY CELLS
[patent_app_type] => utility
[patent_app_number] => 18/664199
[patent_app_country] => US
[patent_app_date] => 2024-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19793
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664199
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/664199 | Programming techniques for polarity-based memory cells | May 13, 2024 | Issued |
Array
(
[id] => 19900045
[patent_doc_number] => 12277977
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-15
[patent_title] => ONON sidewall structure for memory device and method for making the same
[patent_app_type] => utility
[patent_app_number] => 18/662709
[patent_app_country] => US
[patent_app_date] => 2024-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 3556
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18662709
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/662709 | ONON sidewall structure for memory device and method for making the same | May 12, 2024 | Issued |
Array
(
[id] => 19420769
[patent_doc_number] => 20240296893
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-05
[patent_title] => SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/662971
[patent_app_country] => US
[patent_app_date] => 2024-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14159
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18662971
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/662971 | Semiconductor memory device | May 12, 2024 | Issued |
Array
(
[id] => 19900037
[patent_doc_number] => 12277969
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-15
[patent_title] => Auto-referenced memory cell read techniques
[patent_app_type] => utility
[patent_app_number] => 18/661300
[patent_app_country] => US
[patent_app_date] => 2024-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 14701
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18661300
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/661300 | Auto-referenced memory cell read techniques | May 9, 2024 | Issued |
Array
(
[id] => 19574870
[patent_doc_number] => 20240379162
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-14
[patent_title] => NON-VOLATILE MEMORY DEVICES INCLUDING TWISTED BLOCK SELECT LINES
[patent_app_type] => utility
[patent_app_number] => 18/653627
[patent_app_country] => US
[patent_app_date] => 2024-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13746
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18653627
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/653627 | Non-volatile memory devices including twisted block select lines | May 1, 2024 | Issued |
Array
(
[id] => 19559648
[patent_doc_number] => 20240371440
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-07
[patent_title] => CONFIGURATION BIT CIRCUIT FOR PROGRAMMABLE LOGIC DEVICE INCLUDING PHASE CHANGE MEMORY AND OPERATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/651865
[patent_app_country] => US
[patent_app_date] => 2024-05-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4994
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18651865
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/651865 | CONFIGURATION BIT CIRCUIT FOR PROGRAMMABLE LOGIC DEVICE INCLUDING PHASE CHANGE MEMORY AND OPERATION METHOD THEREOF | Apr 30, 2024 | Pending |
Array
(
[id] => 20482645
[patent_doc_number] => 12531121
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-01-20
[patent_title] => Three-dimensional nor memory array of thin-film ferroelectric memory transistors implementing partial polarization
[patent_app_type] => utility
[patent_app_number] => 18/651510
[patent_app_country] => US
[patent_app_date] => 2024-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 29
[patent_no_of_words] => 23496
[patent_no_of_claims] => 43
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 264
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18651510
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/651510 | Three-dimensional nor memory array of thin-film ferroelectric memory transistors implementing partial polarization | Apr 29, 2024 | Issued |
Array
(
[id] => 19406894
[patent_doc_number] => 20240290405
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-29
[patent_title] => SMART PROLOGUE FOR NONVOLATILE MEMORY PROGRAM OPERATION
[patent_app_type] => utility
[patent_app_number] => 18/651261
[patent_app_country] => US
[patent_app_date] => 2024-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13451
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18651261
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/651261 | Smart prologue for nonvolatile memory program operation | Apr 29, 2024 | Issued |
Array
(
[id] => 19781324
[patent_doc_number] => 12230362
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-18
[patent_title] => Memory component with programmable data-to-clock ratio
[patent_app_type] => utility
[patent_app_number] => 18/646059
[patent_app_country] => US
[patent_app_date] => 2024-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 8708
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18646059
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/646059 | Memory component with programmable data-to-clock ratio | Apr 24, 2024 | Issued |
Array
(
[id] => 20538557
[patent_doc_number] => 12555636
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-02-17
[patent_title] => Device mode to improve data retention for NAND MLC technology
[patent_app_type] => utility
[patent_app_number] => 18/643119
[patent_app_country] => US
[patent_app_date] => 2024-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 27
[patent_no_of_words] => 8247
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643119
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/643119 | Device mode to improve data retention for NAND MLC technology | Apr 22, 2024 | Issued |
Array
(
[id] => 20283351
[patent_doc_number] => 20250308593
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-10-02
[patent_title] => Multi-Pass Programming in Memory Devices
[patent_app_type] => utility
[patent_app_number] => 18/639928
[patent_app_country] => US
[patent_app_date] => 2024-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2584
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18639928
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/639928 | Multi-Pass Programming in Memory Devices | Apr 17, 2024 | Pending |
Array
(
[id] => 19986761
[patent_doc_number] => 20250124983
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-17
[patent_title] => MEMORY DEVICES HAVING BUILT-IN POWER SUPPORTING CONTROL CIRCUITS THAT PROVIDE INCREASED PROGRAM AND READ RELIABILITY
[patent_app_type] => utility
[patent_app_number] => 18/637829
[patent_app_country] => US
[patent_app_date] => 2024-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3388
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18637829
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/637829 | Memory devices having built-in power supporting control circuits that provide increased program and read reliability | Apr 16, 2024 | Issued |