Search

Jason Lappas

Examiner (ID: 2641, Phone: (571)270-1272 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
1253
Issued Applications
1140
Pending Applications
50
Abandoned Applications
63

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5918082 [patent_doc_number] => 20020113302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'Semiconductor device' [patent_app_type] => new [patent_app_number] => 09/895025 [patent_app_country] => US [patent_app_date] => 2001-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6269 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20020113302.pdf [firstpage_image] =>[orig_patent_app_number] => 09895025 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/895025
Semiconductor device Jul 1, 2001 Issued
Array ( [id] => 6123539 [patent_doc_number] => 20020074634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Thin, small-sized power semiconductor package' [patent_app_type] => new [patent_app_number] => 09/896120 [patent_app_country] => US [patent_app_date] => 2001-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6606 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20020074634.pdf [firstpage_image] =>[orig_patent_app_number] => 09896120 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/896120
Thin, small-sized power semiconductor package Jul 1, 2001 Issued
Array ( [id] => 6028734 [patent_doc_number] => 20020017677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-14 [patent_title] => 'Semiconductor device having laminated gate structure and method for manufacturing the semiconductor device' [patent_app_type] => new [patent_app_number] => 09/892625 [patent_app_country] => US [patent_app_date] => 2001-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3720 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20020017677.pdf [firstpage_image] =>[orig_patent_app_number] => 09892625 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/892625
Semiconductor device having laminated gate structure and method for manufacturing the semiconductor device Jun 27, 2001 Abandoned
Array ( [id] => 1117009 [patent_doc_number] => 06800947 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-05 [patent_title] => 'Flexible tape electronics packaging' [patent_app_type] => B2 [patent_app_number] => 09/893036 [patent_app_country] => US [patent_app_date] => 2001-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5442 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/800/06800947.pdf [firstpage_image] =>[orig_patent_app_number] => 09893036 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/893036
Flexible tape electronics packaging Jun 26, 2001 Issued
Array ( [id] => 1362430 [patent_doc_number] => 06587999 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-01 [patent_title] => 'Modeling delays for small nets in an integrated circuit design' [patent_app_type] => B1 [patent_app_number] => 09/859149 [patent_app_country] => US [patent_app_date] => 2001-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2448 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/587/06587999.pdf [firstpage_image] =>[orig_patent_app_number] => 09859149 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/859149
Modeling delays for small nets in an integrated circuit design May 14, 2001 Issued
Array ( [id] => 6369796 [patent_doc_number] => 20020059557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-16 [patent_title] => 'Method of forming fine patterns in semiconductor device' [patent_app_type] => new [patent_app_number] => 09/847290 [patent_app_country] => US [patent_app_date] => 2001-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 3925 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20020059557.pdf [firstpage_image] =>[orig_patent_app_number] => 09847290 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/847290
Method of forming fine patterns on semiconductor device May 2, 2001 Issued
Array ( [id] => 707093 [patent_doc_number] => 07065727 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-20 [patent_title] => 'Optimal simultaneous design and floorplanning of integrated circuit' [patent_app_type] => utility [patent_app_number] => 09/843486 [patent_app_country] => US [patent_app_date] => 2001-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3102 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/065/07065727.pdf [firstpage_image] =>[orig_patent_app_number] => 09843486 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/843486
Optimal simultaneous design and floorplanning of integrated circuit Apr 24, 2001 Issued
Array ( [id] => 6593804 [patent_doc_number] => 20020063272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-30 [patent_title] => 'Semiconductor device having a test element, and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/835560 [patent_app_country] => US [patent_app_date] => 2001-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4566 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20020063272.pdf [firstpage_image] =>[orig_patent_app_number] => 09835560 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/835560
Semiconductor device having a test element, and method of manufacturing the same Apr 16, 2001 Issued
Array ( [id] => 6153915 [patent_doc_number] => 20020145186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-10 [patent_title] => 'Method of forming HSQFN type package' [patent_app_type] => new [patent_app_number] => 09/829505 [patent_app_country] => US [patent_app_date] => 2001-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1561 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20020145186.pdf [firstpage_image] =>[orig_patent_app_number] => 09829505 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/829505
Method of forming HSQFN type package Apr 8, 2001 Abandoned
Array ( [id] => 6920572 [patent_doc_number] => 20010028057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-11 [patent_title] => 'Thin-film transistor and method for making the smae' [patent_app_type] => new [patent_app_number] => 09/827676 [patent_app_country] => US [patent_app_date] => 2001-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5011 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20010028057.pdf [firstpage_image] =>[orig_patent_app_number] => 09827676 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/827676
Thin-film transistor and method for making the same Apr 5, 2001 Issued
Array ( [id] => 7626558 [patent_doc_number] => 06768204 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-27 [patent_title] => 'Self-aligned conductive plugs in a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/826185 [patent_app_country] => US [patent_app_date] => 2001-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 36 [patent_no_of_words] => 3739 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/768/06768204.pdf [firstpage_image] =>[orig_patent_app_number] => 09826185 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/826185
Self-aligned conductive plugs in a semiconductor device Apr 4, 2001 Issued
Array ( [id] => 6572880 [patent_doc_number] => 20020014677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-07 [patent_title] => 'Semiconductor device having trench isolation layer and method for manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/826255 [patent_app_country] => US [patent_app_date] => 2001-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2982 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20020014677.pdf [firstpage_image] =>[orig_patent_app_number] => 09826255 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/826255
Semiconductor device having trench isolation layer and method for manufacturing the same Apr 3, 2001 Issued
Array ( [id] => 5840355 [patent_doc_number] => 20020130388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-19 [patent_title] => 'Damascene capacitor having a recessed plate' [patent_app_type] => new [patent_app_number] => 09/811965 [patent_app_country] => US [patent_app_date] => 2001-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3343 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20020130388.pdf [firstpage_image] =>[orig_patent_app_number] => 09811965 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/811965
Damascene capacitor having a recessed plate Mar 18, 2001 Issued
Array ( [id] => 6891228 [patent_doc_number] => 20010017390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-30 [patent_title] => 'Non-uniform gate/dielectric field effect transistor' [patent_app_type] => new [patent_app_number] => 09/808896 [patent_app_country] => US [patent_app_date] => 2001-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4923 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20010017390.pdf [firstpage_image] =>[orig_patent_app_number] => 09808896 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/808896
Non-uniform gate/dielectric field effect transistor Mar 14, 2001 Issued
Array ( [id] => 1330530 [patent_doc_number] => 06600194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-29 [patent_title] => 'Field-effect semiconductor devices' [patent_app_type] => B2 [patent_app_number] => 09/803325 [patent_app_country] => US [patent_app_date] => 2001-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4155 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/600/06600194.pdf [firstpage_image] =>[orig_patent_app_number] => 09803325 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/803325
Field-effect semiconductor devices Mar 8, 2001 Issued
Array ( [id] => 1407315 [patent_doc_number] => 06538325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-25 [patent_title] => 'Multi-layer conductor system with intermediate buffer layer for improved adhesion to dielectrics' [patent_app_type] => B2 [patent_app_number] => 09/799326 [patent_app_country] => US [patent_app_date] => 2001-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 6350 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/538/06538325.pdf [firstpage_image] =>[orig_patent_app_number] => 09799326 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/799326
Multi-layer conductor system with intermediate buffer layer for improved adhesion to dielectrics Mar 5, 2001 Issued
Array ( [id] => 6522689 [patent_doc_number] => 20020109201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-15 [patent_title] => 'Rectifying device and method of fabrication thereof' [patent_app_type] => new [patent_app_number] => 09/779515 [patent_app_country] => US [patent_app_date] => 2001-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2087 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20020109201.pdf [firstpage_image] =>[orig_patent_app_number] => 09779515 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/779515
Rectifying device and method of fabrication thereof Feb 8, 2001 Abandoned
Array ( [id] => 1212751 [patent_doc_number] => 06709945 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-23 [patent_title] => 'Reduced aspect ratio digit line contact process flow used during the formation of a semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/765885 [patent_app_country] => US [patent_app_date] => 2001-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 4048 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/709/06709945.pdf [firstpage_image] =>[orig_patent_app_number] => 09765885 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/765885
Reduced aspect ratio digit line contact process flow used during the formation of a semiconductor device Jan 15, 2001 Issued
Array ( [id] => 6893101 [patent_doc_number] => 20010015467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-23 [patent_title] => 'Transistor for a semiconductor device and method for fabricating same' [patent_app_type] => new [patent_app_number] => 09/751846 [patent_app_country] => US [patent_app_date] => 2001-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1942 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20010015467.pdf [firstpage_image] =>[orig_patent_app_number] => 09751846 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/751846
Transistor for a semiconductor device and method for fabricating same Jan 1, 2001 Abandoned
Array ( [id] => 6876681 [patent_doc_number] => 20010006834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-05 [patent_title] => 'Semiconductor device with high- and low-density regions of transistor elements on single semiconductor substrate, and method of manufacturing such semiconductor device' [patent_app_type] => new-utility [patent_app_number] => 09/741195 [patent_app_country] => US [patent_app_date] => 2000-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 6974 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20010006834.pdf [firstpage_image] =>[orig_patent_app_number] => 09741195 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/741195
Semiconductor device with high- and low-density regions of transistor elements on single semiconductor substrate, and method of manufacturing such semiconductor device Dec 20, 2000 Issued
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