| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 2654629
[patent_doc_number] => 04896263
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-01-23
[patent_title] => 'Multi-microcomputer system'
[patent_app_type] => 1
[patent_app_number] => 7/201343
[patent_app_country] => US
[patent_app_date] => 1988-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2853
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 313
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/896/04896263.pdf
[firstpage_image] =>[orig_patent_app_number] => 201343
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/201343 | Multi-microcomputer system | May 25, 1988 | Issued |
Array
(
[id] => 2691951
[patent_doc_number] => 05046039
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-09-03
[patent_title] => 'Buffer management system'
[patent_app_type] => 1
[patent_app_number] => 7/196540
[patent_app_country] => US
[patent_app_date] => 1988-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 2978
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/046/05046039.pdf
[firstpage_image] =>[orig_patent_app_number] => 196540
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/196540 | Buffer management system | May 19, 1988 | Issued |
Array
(
[id] => 2753263
[patent_doc_number] => 05029124
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-02
[patent_title] => 'Method and apparatus for providing high speed parallel transfer of bursts of data'
[patent_app_type] => 1
[patent_app_number] => 7/195049
[patent_app_country] => US
[patent_app_date] => 1988-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7972
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 370
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/029/05029124.pdf
[firstpage_image] =>[orig_patent_app_number] => 195049
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/195049 | Method and apparatus for providing high speed parallel transfer of bursts of data | May 16, 1988 | Issued |
Array
(
[id] => 2819821
[patent_doc_number] => 05157772
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-10-20
[patent_title] => 'Data bus arrangement with improved speed and timing'
[patent_app_type] => 1
[patent_app_number] => 7/192362
[patent_app_country] => US
[patent_app_date] => 1988-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3494
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/157/05157772.pdf
[firstpage_image] =>[orig_patent_app_number] => 192362
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/192362 | Data bus arrangement with improved speed and timing | May 9, 1988 | Issued |
| 07/189853 | MICROPROCESSOR HAVING EXTERNAL CONTROL STORE | May 2, 1988 | Abandoned |
| 07/174754 | RELIABLE WATCHDOG TIMER | Mar 28, 1988 | Abandoned |
Array
(
[id] => 2765211
[patent_doc_number] => 05043867
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-08-27
[patent_title] => 'Exception reporting mechanism for a vector processor'
[patent_app_type] => 1
[patent_app_number] => 7/170393
[patent_app_country] => US
[patent_app_date] => 1988-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 30
[patent_no_of_words] => 10359
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/043/05043867.pdf
[firstpage_image] =>[orig_patent_app_number] => 170393
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/170393 | Exception reporting mechanism for a vector processor | Mar 17, 1988 | Issued |
Array
(
[id] => 2674471
[patent_doc_number] => 04947477
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-08-07
[patent_title] => 'Partitionable embedded program and data memory for a central processing unit'
[patent_app_type] => 1
[patent_app_number] => 7/164097
[patent_app_country] => US
[patent_app_date] => 1988-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 5816
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 712
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/947/04947477.pdf
[firstpage_image] =>[orig_patent_app_number] => 164097
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/164097 | Partitionable embedded program and data memory for a central processing unit | Mar 3, 1988 | Issued |
| 07/159204 | DIRECT MEMORY ACCESS SYSTEM | Feb 22, 1988 | Abandoned |
Array
(
[id] => 2757579
[patent_doc_number] => 05031095
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-09
[patent_title] => 'Data transmission apparatus'
[patent_app_type] => 1
[patent_app_number] => 7/158199
[patent_app_country] => US
[patent_app_date] => 1988-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 15
[patent_no_of_words] => 6049
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 328
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/031/05031095.pdf
[firstpage_image] =>[orig_patent_app_number] => 158199
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/158199 | Data transmission apparatus | Feb 18, 1988 | Issued |
| 07/155429 | DATA-DRIVEN PROCESSOR | Feb 11, 1988 | Abandoned |
Array
(
[id] => 2481965
[patent_doc_number] => 04879645
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-11-07
[patent_title] => 'Data processing device with high security of stored programs'
[patent_app_type] => 1
[patent_app_number] => 7/157109
[patent_app_country] => US
[patent_app_date] => 1988-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 2466
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/879/04879645.pdf
[firstpage_image] =>[orig_patent_app_number] => 157109
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/157109 | Data processing device with high security of stored programs | Feb 9, 1988 | Issued |
Array
(
[id] => 2499788
[patent_doc_number] => 04860200
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-08-22
[patent_title] => 'Microprocessor interface device for coupling non-compatible protocol peripheral with processor'
[patent_app_type] => 1
[patent_app_number] => 7/144609
[patent_app_country] => US
[patent_app_date] => 1988-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 2755
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/860/04860200.pdf
[firstpage_image] =>[orig_patent_app_number] => 144609
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/144609 | Microprocessor interface device for coupling non-compatible protocol peripheral with processor | Jan 10, 1988 | Issued |
Array
(
[id] => 2821804
[patent_doc_number] => 05086498
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-02-04
[patent_title] => 'Parallel computer with asynchronous communication facility'
[patent_app_type] => 1
[patent_app_number] => 7/145614
[patent_app_country] => US
[patent_app_date] => 1988-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 16
[patent_no_of_words] => 8490
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/086/05086498.pdf
[firstpage_image] =>[orig_patent_app_number] => 145614
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/145614 | Parallel computer with asynchronous communication facility | Jan 9, 1988 | Issued |
Array
(
[id] => 2717304
[patent_doc_number] => 05055999
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-10-08
[patent_title] => 'Multiprocessor digital data processing system'
[patent_app_type] => 1
[patent_app_number] => 7/136930
[patent_app_country] => US
[patent_app_date] => 1987-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 14
[patent_no_of_words] => 18592
[patent_no_of_claims] => 68
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/055/05055999.pdf
[firstpage_image] =>[orig_patent_app_number] => 136930
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/136930 | Multiprocessor digital data processing system | Dec 21, 1987 | Issued |
| 07/135546 | DATA PROCESSING SYSTEM USING STREAM STORES | Dec 17, 1987 | Abandoned |
| 07/133092 | REDUCED INSTRUCTION SET COMPUTER SYSTEM INCLUDING APPARATUS AND METHODS FOR COUPLING A HIGH PERFORMANCE RISC INTERFACE TO A PERIPHERAL BUS HAVING DIFFERENT PERFORMANCE CHARACTERISTICS | Dec 14, 1987 | Abandoned |
Array
(
[id] => 2689239
[patent_doc_number] => 05067105
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-11-19
[patent_title] => 'System and method for automatically configuring translation of logical addresses to a physical memory address in a computer memory system'
[patent_app_type] => 1
[patent_app_number] => 7/120884
[patent_app_country] => US
[patent_app_date] => 1987-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1872
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/067/05067105.pdf
[firstpage_image] =>[orig_patent_app_number] => 120884
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/120884 | System and method for automatically configuring translation of logical addresses to a physical memory address in a computer memory system | Nov 15, 1987 | Issued |
| 07/117564 | HIGHLY PARALLEL COMPUTER ARCHITECTURE EMPLOYING CROSSBAR SWITCH WITH SELECTABLE PIPELINE DELAY | Nov 5, 1987 | Abandoned |
Array
(
[id] => 2731491
[patent_doc_number] => 05025414
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-06-18
[patent_title] => 'Serial bus interface capable of transferring data in different formats'
[patent_app_type] => 1
[patent_app_number] => 7/117738
[patent_app_country] => US
[patent_app_date] => 1987-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3169
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/025/05025414.pdf
[firstpage_image] =>[orig_patent_app_number] => 117738
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/117738 | Serial bus interface capable of transferring data in different formats | Nov 5, 1987 | Issued |