Search

Jason S Morrow

Examiner (ID: 17033, Phone: (571)272-6663 , Office: P/3612 )

Most Active Art Unit
3612
Art Unit(s)
3612
Total Applications
2528
Issued Applications
2072
Pending Applications
145
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11291862 [patent_doc_number] => 20160341795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-24 [patent_title] => 'Scheme for Masking Output of Scan Chains in Test Circuit' [patent_app_type] => utility [patent_app_number] => 15/230860 [patent_app_country] => US [patent_app_date] => 2016-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7281 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15230860 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/230860
Scheme for Masking Output of Scan Chains in Test Circuit Aug 7, 2016 Abandoned
Array ( [id] => 11118751 [patent_doc_number] => 20160315725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-27 [patent_title] => 'METHOD AND APPARATUS FOR TRANSMITTING DATA IN OPTICAL TRANSPORT NETWORK' [patent_app_type] => utility [patent_app_number] => 15/198535 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 6935 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15198535 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/198535
METHOD AND APPARATUS FOR TRANSMITTING DATA IN OPTICAL TRANSPORT NETWORK Jun 29, 2016 Abandoned
Array ( [id] => 14511437 [patent_doc_number] => 20190199373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => METHOD AND APPARATUS FOR GENERATING QUANTUM ERROR CORRECTION CODE USING GRAPH STATE [patent_app_type] => utility [patent_app_number] => 16/309281 [patent_app_country] => US [patent_app_date] => 2016-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6510 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16309281 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/309281
Method and apparatus for generating quantum error correction code using graph state Jun 23, 2016 Issued
Array ( [id] => 12983815 [patent_doc_number] => 20170343601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => BUILT-IN DEVICE TESTING OF INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 15/166578 [patent_app_country] => US [patent_app_date] => 2016-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6139 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15166578 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/166578
Built-in device testing of integrated circuits May 26, 2016 Issued
Array ( [id] => 15471133 [patent_doc_number] => 10551435 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-02-04 [patent_title] => 2D compression-based low power ATPG [patent_app_type] => utility [patent_app_number] => 15/163351 [patent_app_country] => US [patent_app_date] => 2016-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 5730 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15163351 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/163351
2D compression-based low power ATPG May 23, 2016 Issued
Array ( [id] => 14616577 [patent_doc_number] => 10360992 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Test devices and test systems [patent_app_type] => utility [patent_app_number] => 15/157799 [patent_app_country] => US [patent_app_date] => 2016-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 10548 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15157799 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/157799
Test devices and test systems May 17, 2016 Issued
Array ( [id] => 12052607 [patent_doc_number] => 20170328951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-16 [patent_title] => 'EMBEDDED BUILT-IN SELF-TEST (BIST) CIRCUITRY FOR DIGITAL SIGNAL PROCESSOR (DSP) VALIDATION' [patent_app_type] => utility [patent_app_number] => 15/154266 [patent_app_country] => US [patent_app_date] => 2016-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6817 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15154266 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/154266
EMBEDDED BUILT-IN SELF-TEST (BIST) CIRCUITRY FOR DIGITAL SIGNAL PROCESSOR (DSP) VALIDATION May 12, 2016 Abandoned
Array ( [id] => 16480450 [patent_doc_number] => 10855413 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Method and apparatus for evaluating and optimizing a signaling system [patent_app_type] => utility [patent_app_number] => 15/143299 [patent_app_country] => US [patent_app_date] => 2016-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 34 [patent_no_of_words] => 20095 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15143299 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/143299
Method and apparatus for evaluating and optimizing a signaling system Apr 28, 2016 Issued
Array ( [id] => 11891693 [patent_doc_number] => 09762264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-12 [patent_title] => 'Transmitting apparatus and interleaving method thereof' [patent_app_type] => utility [patent_app_number] => 15/099946 [patent_app_country] => US [patent_app_date] => 2016-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 41848 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15099946 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/099946
Transmitting apparatus and interleaving method thereof Apr 14, 2016 Issued
Array ( [id] => 13554881 [patent_doc_number] => 20180328988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => CONTROLLING A TRANSITION BETWEEN A FUNCTIONAL MODE AND A TEST MODE [patent_app_type] => utility [patent_app_number] => 15/775734 [patent_app_country] => US [patent_app_date] => 2016-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4298 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15775734 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/775734
CONTROLLING A TRANSITION BETWEEN A FUNCTIONAL MODE AND A TEST MODE Mar 15, 2016 Abandoned
Array ( [id] => 15428777 [patent_doc_number] => 10547329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-28 [patent_title] => Transmitter and puncturing method thereof [patent_app_type] => utility [patent_app_number] => 15/058364 [patent_app_country] => US [patent_app_date] => 2016-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 29138 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15058364 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/058364
Transmitter and puncturing method thereof Mar 1, 2016 Issued
Array ( [id] => 11069242 [patent_doc_number] => 20160266205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-15 [patent_title] => 'LOGIC VERIFICATION APPARATUS, LOGIC VERIFICATION METHOD AND TEST PROGRAM' [patent_app_type] => utility [patent_app_number] => 15/048334 [patent_app_country] => US [patent_app_date] => 2016-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 14794 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15048334 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/048334
LOGIC VERIFICATION APPARATUS, LOGIC VERIFICATION METHOD AND TEST PROGRAM Feb 18, 2016 Abandoned
Array ( [id] => 11938597 [patent_doc_number] => 20170242747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'ERROR RATE REDUCTION' [patent_app_type] => utility [patent_app_number] => 15/046666 [patent_app_country] => US [patent_app_date] => 2016-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7685 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15046666 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/046666
Error rate reduction Feb 17, 2016 Issued
Array ( [id] => 11044402 [patent_doc_number] => 20160241357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'TRANSMITTER AND ADDITIONAL PARITY GENERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/044419 [patent_app_country] => US [patent_app_date] => 2016-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 65 [patent_figures_cnt] => 65 [patent_no_of_words] => 40146 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15044419 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/044419
Transmitter and additional parity generating method thereof Feb 15, 2016 Issued
Array ( [id] => 14708589 [patent_doc_number] => 10382064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Efficient LDPC encoder for irregular code [patent_app_type] => utility [patent_app_number] => 15/018682 [patent_app_country] => US [patent_app_date] => 2016-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4925 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15018682 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/018682
Efficient LDPC encoder for irregular code Feb 7, 2016 Issued
Array ( [id] => 13349193 [patent_doc_number] => 20180226136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => SYSTEM MANAGEMENT MODE TEST OPERATIONS [patent_app_type] => utility [patent_app_number] => 15/749114 [patent_app_country] => US [patent_app_date] => 2016-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4580 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15749114 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/749114
SYSTEM MANAGEMENT MODE TEST OPERATIONS Jan 26, 2016 Abandoned
Array ( [id] => 11133014 [patent_doc_number] => 20160329989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-10 [patent_title] => 'High-efficiency wireless preamble structures with efficient cyclic redundancy check' [patent_app_type] => utility [patent_app_number] => 14/757961 [patent_app_country] => US [patent_app_date] => 2015-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 25408 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14757961 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/757961
High-efficiency wireless preamble structures with efficient cyclic redundancy check Dec 25, 2015 Abandoned
Array ( [id] => 13005665 [patent_doc_number] => 10026503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => Program and operating methods of nonvolatile memory device [patent_app_type] => utility [patent_app_number] => 14/956659 [patent_app_country] => US [patent_app_date] => 2015-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 14085 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14956659 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/956659
Program and operating methods of nonvolatile memory device Dec 1, 2015 Issued
Array ( [id] => 13529643 [patent_doc_number] => 20180316364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => METHODS, SYSTEMS, AND COMPUTER-READABLE MEDIA FOR DECODING A CYCLIC CODE [patent_app_type] => utility [patent_app_number] => 15/772059 [patent_app_country] => US [patent_app_date] => 2015-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10814 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15772059 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/772059
Methods, systems, and computer-readable media for decoding a cyclic code Nov 1, 2015 Issued
Array ( [id] => 12032743 [patent_doc_number] => 20170322842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-09 [patent_title] => 'MEMORY CONTROLLER, MEMORY SYSTEM, AND METHOD OF CONTROLLING MEMORY CONTROLLER' [patent_app_type] => utility [patent_app_number] => 15/529697 [patent_app_country] => US [patent_app_date] => 2015-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 10620 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15529697 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/529697
MEMORY CONTROLLER, MEMORY SYSTEM, AND METHOD OF CONTROLLING MEMORY CONTROLLER Oct 7, 2015 Abandoned
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