Search

Jason S Morrow

Examiner (ID: 17033, Phone: (571)272-6663 , Office: P/3612 )

Most Active Art Unit
3612
Art Unit(s)
3612
Total Applications
2528
Issued Applications
2072
Pending Applications
145
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12250785 [patent_doc_number] => 09923576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-20 [patent_title] => 'Decoding techniques using a programmable priority encoder' [patent_app_type] => utility [patent_app_number] => 14/487475 [patent_app_country] => US [patent_app_date] => 2014-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6692 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14487475 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/487475
Decoding techniques using a programmable priority encoder Sep 15, 2014 Issued
Array ( [id] => 10376595 [patent_doc_number] => 20150261602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'RESISTANCE CHANGE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/482968 [patent_app_country] => US [patent_app_date] => 2014-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4319 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14482968 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/482968
RESISTANCE CHANGE MEMORY Sep 9, 2014 Abandoned
Array ( [id] => 13863661 [patent_doc_number] => 10193569 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-29 [patent_title] => Decoding method, memory storage device and memory control circuit unit [patent_app_type] => utility [patent_app_number] => 14/477867 [patent_app_country] => US [patent_app_date] => 2014-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 10886 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14477867 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/477867
Decoding method, memory storage device and memory control circuit unit Sep 4, 2014 Issued
Array ( [id] => 11014914 [patent_doc_number] => 20160211866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'DATA PROCESSING DEVICE AND DATA PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 14/913566 [patent_app_country] => US [patent_app_date] => 2014-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 56 [patent_no_of_words] => 37727 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14913566 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/913566
DATA PROCESSING DEVICE AND DATA PROCESSING METHOD Sep 4, 2014 Abandoned
Array ( [id] => 11801388 [patent_doc_number] => 09542265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-10 [patent_title] => 'Unequal error protection scheme for headerized sub data sets' [patent_app_type] => utility [patent_app_number] => 14/477647 [patent_app_country] => US [patent_app_date] => 2014-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 11836 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14477647 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/477647
Unequal error protection scheme for headerized sub data sets Sep 3, 2014 Issued
Array ( [id] => 10464910 [patent_doc_number] => 20150349926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'MESSAGES WITH ATTENUATING RETRANSMIT IMPORTANCE' [patent_app_type] => utility [patent_app_number] => 14/475496 [patent_app_country] => US [patent_app_date] => 2014-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 16221 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14475496 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/475496
Messages with attenuating retransmit importance Sep 1, 2014 Issued
Array ( [id] => 10320523 [patent_doc_number] => 20150205527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'ZERO-ONE BALANCE MANAGEMENT IN A SOLID-STATE DISK CONTROLLER' [patent_app_type] => utility [patent_app_number] => 14/472869 [patent_app_country] => US [patent_app_date] => 2014-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 19453 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14472869 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/472869
Zero-one balance management in a solid-state disk controller Aug 28, 2014 Issued
Array ( [id] => 10716680 [patent_doc_number] => 20160062827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND PROGRAMMING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/470948 [patent_app_country] => US [patent_app_date] => 2014-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5828 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14470948 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/470948
Semiconductor memory device and programming method thereof Aug 27, 2014 Issued
Array ( [id] => 11222262 [patent_doc_number] => 09450612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-20 [patent_title] => 'Encoding method and system for quasi-cyclic low-density parity-check code' [patent_app_type] => utility [patent_app_number] => 14/454996 [patent_app_country] => US [patent_app_date] => 2014-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7719 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14454996 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/454996
Encoding method and system for quasi-cyclic low-density parity-check code Aug 7, 2014 Issued
Array ( [id] => 9866756 [patent_doc_number] => 20150046775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => 'Encoding and Decoding Schemes to Achieve Standard Compliant Mean Time to False Packet Acceptance' [patent_app_type] => utility [patent_app_number] => 14/454393 [patent_app_country] => US [patent_app_date] => 2014-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6925 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14454393 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/454393
Encoding and Decoding Schemes to Achieve Standard Compliant Mean Time to False Packet Acceptance Aug 6, 2014 Abandoned
Array ( [id] => 10690322 [patent_doc_number] => 20160036468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-04 [patent_title] => 'METHOD AND DEVICE FOR ITERATIVE DECODING A DATA TRANSFER STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/449554 [patent_app_country] => US [patent_app_date] => 2014-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7329 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14449554 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/449554
METHOD AND DEVICE FOR ITERATIVE DECODING A DATA TRANSFER STRUCTURE Jul 31, 2014 Abandoned
Array ( [id] => 10651134 [patent_doc_number] => 09367386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-14 [patent_title] => 'Semiconductor integrated circuit and drive apparatus including the same' [patent_app_type] => utility [patent_app_number] => 14/330797 [patent_app_country] => US [patent_app_date] => 2014-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 65 [patent_figures_cnt] => 67 [patent_no_of_words] => 23140 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14330797 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/330797
Semiconductor integrated circuit and drive apparatus including the same Jul 13, 2014 Issued
Array ( [id] => 9903499 [patent_doc_number] => 20150058699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-26 [patent_title] => 'Methods for Accessing a Storage Unit of a Flash Memory and Apparatuses using the Same' [patent_app_type] => utility [patent_app_number] => 14/330866 [patent_app_country] => US [patent_app_date] => 2014-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 11148 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14330866 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/330866
Methods for accessing a storage unit of a flash memory and apparatuses using the same Jul 13, 2014 Issued
Array ( [id] => 10660314 [patent_doc_number] => 20160006458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-07 [patent_title] => 'DECODING TECHNIQUES FOR LOW-DENSITY PARITY CHECK CODES' [patent_app_type] => utility [patent_app_number] => 14/321069 [patent_app_country] => US [patent_app_date] => 2014-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13379 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14321069 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/321069
DECODING TECHNIQUES FOR LOW-DENSITY PARITY CHECK CODES Jun 30, 2014 Abandoned
Array ( [id] => 9930235 [patent_doc_number] => 20150078426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-19 [patent_title] => 'Method And Apparatus For Evaluating And Optimizing A Signaling System' [patent_app_type] => utility [patent_app_number] => 14/318557 [patent_app_country] => US [patent_app_date] => 2014-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 20370 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14318557 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/318557
Method and apparatus for evaluating and optimizing a signaling system Jun 26, 2014 Issued
Array ( [id] => 9800859 [patent_doc_number] => 20150012804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-08 [patent_title] => 'TRANSMITTING APPARATUS, ENCODING METHOD THEREOF, RECEIVING APPARATUS, AND DECODING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/308977 [patent_app_country] => US [patent_app_date] => 2014-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 11601 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14308977 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/308977
Transmitting apparatus, encoding method thereof, receiving apparatus, and decoding method thereof Jun 18, 2014 Issued
Array ( [id] => 10969798 [patent_doc_number] => 20140372831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-18 [patent_title] => 'MEMORY CONTROLLER OPERATING METHOD FOR READ OPERATIONS IN SYSTEM HAVING NONVOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/303646 [patent_app_country] => US [patent_app_date] => 2014-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6285 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14303646 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/303646
MEMORY CONTROLLER OPERATING METHOD FOR READ OPERATIONS IN SYSTEM HAVING NONVOLATILE MEMORY DEVICE Jun 12, 2014 Abandoned
Array ( [id] => 10408800 [patent_doc_number] => 20150293809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'DATA STORING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/297649 [patent_app_country] => US [patent_app_date] => 2014-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12876 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14297649 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/297649
Data storing method, memory control circuit unit and memory storage apparatus Jun 5, 2014 Issued
Array ( [id] => 11252803 [patent_doc_number] => 09478315 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-25 [patent_title] => 'Bit error rate mapping in a memory system' [patent_app_type] => utility [patent_app_number] => 14/294864 [patent_app_country] => US [patent_app_date] => 2014-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7156 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14294864 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/294864
Bit error rate mapping in a memory system Jun 2, 2014 Issued
Array ( [id] => 9903485 [patent_doc_number] => 20150058685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-26 [patent_title] => 'METHOD AND SYSTEM OF TESTING SEMICONDUCTOR MEMORY' [patent_app_type] => utility [patent_app_number] => 14/293983 [patent_app_country] => US [patent_app_date] => 2014-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4097 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14293983 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/293983
METHOD AND SYSTEM OF TESTING SEMICONDUCTOR MEMORY Jun 1, 2014 Abandoned
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