Search

Jason S Morrow

Examiner (ID: 17033, Phone: (571)272-6663 , Office: P/3612 )

Most Active Art Unit
3612
Art Unit(s)
3612
Total Applications
2528
Issued Applications
2072
Pending Applications
145
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18489256 [patent_doc_number] => 20230216607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => SYSTEMS AND METHODS TO INITIATE DEVICE RECOVERY [patent_app_type] => utility [patent_app_number] => 17/566591 [patent_app_country] => US [patent_app_date] => 2021-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7565 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17566591 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/566591
SYSTEMS AND METHODS TO INITIATE DEVICE RECOVERY Dec 29, 2021 Pending
Array ( [id] => 18472750 [patent_doc_number] => 20230207038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => DRAM SPECIFIC INTERFACE CALIBRATION VIA PROGRAMMABLE TRAINING SEQUENCES [patent_app_type] => utility [patent_app_number] => 17/564327 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6302 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564327 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/564327
DRAM SPECIFIC INTERFACE CALIBRATION VIA PROGRAMMABLE TRAINING SEQUENCES Dec 28, 2021 Pending
Array ( [id] => 17508835 [patent_doc_number] => 20220101938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => MEMORY SYSTEM TESTER USING TEST PAD REAL TIME MONITORING [patent_app_type] => utility [patent_app_number] => 17/549377 [patent_app_country] => US [patent_app_date] => 2021-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18905 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17549377 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/549377
Memory system tester using test pad real time monitoring Dec 12, 2021 Issued
Array ( [id] => 19442434 [patent_doc_number] => 12092689 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Scan test in a single-wire bus circuit [patent_app_type] => utility [patent_app_number] => 17/545113 [patent_app_country] => US [patent_app_date] => 2021-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6479 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17545113 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/545113
Scan test in a single-wire bus circuit Dec 7, 2021 Issued
Array ( [id] => 18423645 [patent_doc_number] => 20230178109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => COMPOSITE DATA RECOVERY PROCEDURE [patent_app_type] => utility [patent_app_number] => 17/542875 [patent_app_country] => US [patent_app_date] => 2021-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10657 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17542875 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/542875
Composite data recovery procedure Dec 5, 2021 Issued
Array ( [id] => 17447925 [patent_doc_number] => 20220068430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => APPARATUSES AND METHODS FOR REPAIRING DEFECTIVE MEMORY CELLS BASED ON A SPECIFIED ERROR RATE FOR CERTAIN MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/454443 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9172 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17454443 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/454443
Apparatuses and methods for repairing defective memory cells based on a specified error rate for certain memory cells Nov 9, 2021 Issued
Array ( [id] => 17416843 [patent_doc_number] => 20220051747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => PROGRAM AND OPERATING METHODS OF NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/513233 [patent_app_country] => US [patent_app_date] => 2021-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14172 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17513233 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/513233
Program and operating methods of nonvolatile memory device Oct 27, 2021 Issued
Array ( [id] => 18336517 [patent_doc_number] => 20230128466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => AUTOMATIC TEST PATTERN GENERATION CIRCUITRY IN MULTI POWER DOMAIN SYSTEM ON A CHIP [patent_app_type] => utility [patent_app_number] => 17/510602 [patent_app_country] => US [patent_app_date] => 2021-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5634 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17510602 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/510602
Automatic test pattern generation circuitry in multi power domain system on a chip Oct 25, 2021 Issued
Array ( [id] => 17523675 [patent_doc_number] => 20220109524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-07 [patent_title] => POLAR CODE ENCODING METHOD AND APPARATUS IN WIRELESS COMMUNICATIONS [patent_app_type] => utility [patent_app_number] => 17/491529 [patent_app_country] => US [patent_app_date] => 2021-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 78993 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17491529 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/491529
Polar code encoding method and apparatus in wireless communications Sep 30, 2021 Issued
Array ( [id] => 18269250 [patent_doc_number] => 20230090492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => RATE MATCHING AND CHANNEL INTERLEAVING FOR PROBABILISTIC SHAPING [patent_app_type] => utility [patent_app_number] => 17/482315 [patent_app_country] => US [patent_app_date] => 2021-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18692 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17482315 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/482315
Rate matching and channel interleaving for probabilistic shaping Sep 21, 2021 Issued
Array ( [id] => 19243315 [patent_doc_number] => 12013754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Nonvolatile memory device and memory system including nonvolatile memory device [patent_app_type] => utility [patent_app_number] => 17/479067 [patent_app_country] => US [patent_app_date] => 2021-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11631 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17479067 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/479067
Nonvolatile memory device and memory system including nonvolatile memory device Sep 19, 2021 Issued
Array ( [id] => 18414212 [patent_doc_number] => 11668750 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Performing testing utilizing staggered clocks [patent_app_type] => utility [patent_app_number] => 17/478736 [patent_app_country] => US [patent_app_date] => 2021-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11176 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17478736 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/478736
Performing testing utilizing staggered clocks Sep 16, 2021 Issued
Array ( [id] => 18780234 [patent_doc_number] => 11821946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Built in self test (BIST) for clock generation circuitry [patent_app_type] => utility [patent_app_number] => 17/447743 [patent_app_country] => US [patent_app_date] => 2021-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6321 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17447743 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/447743
Built in self test (BIST) for clock generation circuitry Sep 14, 2021 Issued
Array ( [id] => 17582622 [patent_doc_number] => 20220139477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => METHOD AND CIRCUIT FOR ROW SCANNABLE LATCH ARRAY [patent_app_type] => utility [patent_app_number] => 17/468024 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8264 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17468024 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/468024
Method and circuit for row scannable latch array Sep 6, 2021 Issued
Array ( [id] => 17582623 [patent_doc_number] => 20220139478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => METHOD AND CIRCUIT FOR SCAN DUMP OF LATCH ARRAY [patent_app_type] => utility [patent_app_number] => 17/468066 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8231 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17468066 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/468066
Method and circuit for scan dump of latch array Sep 6, 2021 Issued
Array ( [id] => 18527724 [patent_doc_number] => 11714716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => 3-dimensional NAND flash layer variation aware SSD raid [patent_app_type] => utility [patent_app_number] => 17/461482 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7197 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461482 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461482
3-dimensional NAND flash layer variation aware SSD raid Aug 29, 2021 Issued
Array ( [id] => 17746313 [patent_doc_number] => 11394403 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-07-19 [patent_title] => Error correction based on rate adaptive low density parity check (LDPC) codes with flexible column weights in the parity check matrices [patent_app_type] => utility [patent_app_number] => 17/409359 [patent_app_country] => US [patent_app_date] => 2021-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8288 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17409359 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/409359
Error correction based on rate adaptive low density parity check (LDPC) codes with flexible column weights in the parity check matrices Aug 22, 2021 Issued
Array ( [id] => 17861653 [patent_doc_number] => 11442811 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-13 [patent_title] => Apparatus and method for using an error correction code in a memory system [patent_app_type] => utility [patent_app_number] => 17/378176 [patent_app_country] => US [patent_app_date] => 2021-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 20078 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17378176 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/378176
Apparatus and method for using an error correction code in a memory system Jul 15, 2021 Issued
Array ( [id] => 18446008 [patent_doc_number] => 11681579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-20 [patent_title] => Semiconductor memory devices and memory systems including the same [patent_app_type] => utility [patent_app_number] => 17/344180 [patent_app_country] => US [patent_app_date] => 2021-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 10089 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17344180 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/344180
Semiconductor memory devices and memory systems including the same Jun 9, 2021 Issued
Array ( [id] => 18175666 [patent_doc_number] => 11575392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Transmitting apparatus and signal processing method thereof [patent_app_type] => utility [patent_app_number] => 17/333101 [patent_app_country] => US [patent_app_date] => 2021-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 34443 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17333101 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/333101
Transmitting apparatus and signal processing method thereof May 27, 2021 Issued
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