Jason S Morrow
Examiner (ID: 17033, Phone: (571)272-6663 , Office: P/3612 )
Most Active Art Unit | 3612 |
Art Unit(s) | 3612 |
Total Applications | 2528 |
Issued Applications | 2072 |
Pending Applications | 145 |
Abandoned Applications | 311 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 16545973
[patent_doc_number] => 20200412388
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-31
[patent_title] => RESIDUE CHECKING OF ENTIRE NORMALIZER OUTPUT OF AN EXTENDED RESULT
[patent_app_type] => utility
[patent_app_number] => 16/453395
[patent_app_country] => US
[patent_app_date] => 2019-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4165
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16453395
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/453395 | Residue checking of entire normalizer output of an extended result | Jun 25, 2019 | Issued |
Array
(
[id] => 16544717
[patent_doc_number] => 20200411132
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-31
[patent_title] => APPARATUSES AND METHODS FOR REPAIRING DEFECTIVE MEMORY CELLS BASED ON A SPECIFIED ERROR RATE FOR CERTAIN MEMORY CELLS
[patent_app_type] => utility
[patent_app_number] => 16/453905
[patent_app_country] => US
[patent_app_date] => 2019-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9136
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -24
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16453905
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/453905 | Apparatuses and methods for repairing defective memory cells based on a specified error rate for certain memory cells | Jun 25, 2019 | Issued |
Array
(
[id] => 14940491
[patent_doc_number] => 20190305884
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-03
[patent_title] => METHODS AND SYSTEMS FOR DATA TRANSMISSION
[patent_app_type] => utility
[patent_app_number] => 16/444421
[patent_app_country] => US
[patent_app_date] => 2019-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5758
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16444421
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/444421 | Methods and systems for data transmission | Jun 17, 2019 | Issued |
Array
(
[id] => 17188520
[patent_doc_number] => 20210335405
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-28
[patent_title] => MEMORY DEVICE HAVING AN ENHANCED ESD PROTECTION AND A SECURE ACCESS FROM A TESTING MACHINE
[patent_app_type] => utility
[patent_app_number] => 16/625080
[patent_app_country] => US
[patent_app_date] => 2019-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5017
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16625080
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/625080 | Memory device having an enhanced ESD protection and a secure access from a testing machine | May 30, 2019 | Issued |
Array
(
[id] => 14844639
[patent_doc_number] => 20190280720
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-09-12
[patent_title] => TRANSMITTING APPARATUS AND SIGNAL PROCESSING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/424466
[patent_app_country] => US
[patent_app_date] => 2019-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 35317
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 262
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16424466
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/424466 | Transmitting apparatus and signal processing method thereof | May 27, 2019 | Issued |
Array
(
[id] => 18506361
[patent_doc_number] => 11704178
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-07-18
[patent_title] => Estimating a bit error rate of data stored by a memory subsystem using machine learning
[patent_app_type] => utility
[patent_app_number] => 16/412325
[patent_app_country] => US
[patent_app_date] => 2019-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7933
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16412325
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/412325 | Estimating a bit error rate of data stored by a memory subsystem using machine learning | May 13, 2019 | Issued |
Array
(
[id] => 14997799
[patent_doc_number] => 20190317857
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-17
[patent_title] => TECHNOLOGIES FOR PROVIDING ERROR CORRECTION FOR ROW DIRECTION AND COLUMN DIRECTION IN A CROSS POINT MEMORY
[patent_app_type] => utility
[patent_app_number] => 16/395769
[patent_app_country] => US
[patent_app_date] => 2019-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8770
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16395769
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/395769 | TECHNOLOGIES FOR PROVIDING ERROR CORRECTION FOR ROW DIRECTION AND COLUMN DIRECTION IN A CROSS POINT MEMORY | Apr 25, 2019 | Abandoned |
Array
(
[id] => 16744999
[patent_doc_number] => 10969987
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-04-06
[patent_title] => Memory device, memory system including the memory device, and method of operating the memory system
[patent_app_type] => utility
[patent_app_number] => 16/395890
[patent_app_country] => US
[patent_app_date] => 2019-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 13
[patent_no_of_words] => 8297
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16395890
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/395890 | Memory device, memory system including the memory device, and method of operating the memory system | Apr 25, 2019 | Issued |
Array
(
[id] => 14724255
[patent_doc_number] => 20190253191
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-15
[patent_title] => TRANSMITTING APPARATUS AND SIGNAL PROCESSING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/390764
[patent_app_country] => US
[patent_app_date] => 2019-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 35449
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -3
[patent_words_short_claim] => 214
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16390764
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/390764 | Transmitting apparatus and signal processing method thereof | Apr 21, 2019 | Issued |
Array
(
[id] => 16699717
[patent_doc_number] => 10950325
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-16
[patent_title] => Memory built-in self test error correcting code (MBIST ECC) for low voltage memories
[patent_app_type] => utility
[patent_app_number] => 16/375115
[patent_app_country] => US
[patent_app_date] => 2019-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6195
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 214
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16375115
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/375115 | Memory built-in self test error correcting code (MBIST ECC) for low voltage memories | Apr 3, 2019 | Issued |
Array
(
[id] => 16767384
[patent_doc_number] => 10979177
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-04-13
[patent_title] => Method for identifying data corruption in a data transfer over an error-proof communication link
[patent_app_type] => utility
[patent_app_number] => 16/374941
[patent_app_country] => US
[patent_app_date] => 2019-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 2720
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16374941
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/374941 | Method for identifying data corruption in a data transfer over an error-proof communication link | Apr 3, 2019 | Issued |
Array
(
[id] => 17091507
[patent_doc_number] => 11119695
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-09-14
[patent_title] => Memory dispatcher
[patent_app_type] => utility
[patent_app_number] => 16/367694
[patent_app_country] => US
[patent_app_date] => 2019-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4921
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16367694
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/367694 | Memory dispatcher | Mar 27, 2019 | Issued |
Array
(
[id] => 16314658
[patent_doc_number] => 20200293396
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-17
[patent_title] => DEFERRED ERROR CODE CORRECTION WITH IMPROVED EFFECTIVE DATA BANDWIDTH PERFORMANCE
[patent_app_type] => utility
[patent_app_number] => 16/353962
[patent_app_country] => US
[patent_app_date] => 2019-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5571
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16353962
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/353962 | Deferred error code correction with improved effective data bandwidth performance | Mar 13, 2019 | Issued |
Array
(
[id] => 16972372
[patent_doc_number] => 11068344
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-07-20
[patent_title] => Candidate bit detection and utilization for error correction
[patent_app_type] => utility
[patent_app_number] => 16/352783
[patent_app_country] => US
[patent_app_date] => 2019-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 9766
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16352783
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/352783 | Candidate bit detection and utilization for error correction | Mar 12, 2019 | Issued |
Array
(
[id] => 17040388
[patent_doc_number] => 20210257024
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-19
[patent_title] => STORAGE CONTROL DEVICE, STORAGE DEVICE, AND STORAGE CONTROL METHOD
[patent_app_type] => utility
[patent_app_number] => 17/250202
[patent_app_country] => US
[patent_app_date] => 2019-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13700
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17250202
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/250202 | STORAGE CONTROL DEVICE, STORAGE DEVICE, AND STORAGE CONTROL METHOD | Mar 4, 2019 | Abandoned |
Array
(
[id] => 16271052
[patent_doc_number] => 20200272540
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-08-27
[patent_title] => 3-DIMENSIONAL NAND FLASH LAYER VARIATION AWARE SSD RAID
[patent_app_type] => utility
[patent_app_number] => 16/287251
[patent_app_country] => US
[patent_app_date] => 2019-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7207
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16287251
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/287251 | 3-dimensional NAND flash layer variation aware SSD raid | Feb 26, 2019 | Issued |
Array
(
[id] => 15624987
[patent_doc_number] => 20200082898
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-12
[patent_title] => MULTI-LVEL MEMORY HIERARCHY
[patent_app_type] => utility
[patent_app_number] => 16/287727
[patent_app_country] => US
[patent_app_date] => 2019-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3685
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16287727
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/287727 | Multi-level memory hierarchy | Feb 26, 2019 | Issued |
Array
(
[id] => 15621317
[patent_doc_number] => 20200081063
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-12
[patent_title] => TEST CIRCUIT AND TEST METHOD
[patent_app_type] => utility
[patent_app_number] => 16/286867
[patent_app_country] => US
[patent_app_date] => 2019-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4687
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16286867
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/286867 | TEST CIRCUIT AND TEST METHOD | Feb 26, 2019 | Abandoned |
Array
(
[id] => 15719561
[patent_doc_number] => 20200106548
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-02
[patent_title] => METHOD AND APPARATUS FOR ANALYSIS OF SPECTRUM USE STATUS
[patent_app_type] => utility
[patent_app_number] => 16/275096
[patent_app_country] => US
[patent_app_date] => 2019-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9166
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 42
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16275096
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/275096 | Method and apparatus for analysis of spectrum use status | Feb 12, 2019 | Issued |
Array
(
[id] => 16638671
[patent_doc_number] => 10917196
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-02-09
[patent_title] => Efficient transmission of small packets in low power and lossy networks
[patent_app_type] => utility
[patent_app_number] => 16/273251
[patent_app_country] => US
[patent_app_date] => 2019-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7916
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16273251
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/273251 | Efficient transmission of small packets in low power and lossy networks | Feb 11, 2019 | Issued |