Search

Jason Y. Ko

Examiner (ID: 1948)

Most Active Art Unit
1711
Art Unit(s)
1792, 1711
Total Applications
1498
Issued Applications
1154
Pending Applications
89
Abandoned Applications
287

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 879735 [patent_doc_number] => 07354805 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-08 [patent_title] => 'Method of making electrically programmable fuse for silicon-on-insulator (SOI) technology' [patent_app_type] => utility [patent_app_number] => 11/739979 [patent_app_country] => US [patent_app_date] => 2007-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 3582 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/354/07354805.pdf [firstpage_image] =>[orig_patent_app_number] => 11739979 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/739979
Method of making electrically programmable fuse for silicon-on-insulator (SOI) technology Apr 24, 2007 Issued
Array ( [id] => 823984 [patent_doc_number] => 07405457 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-29 [patent_title] => 'High temperature thermistors' [patent_app_type] => utility [patent_app_number] => 11/788440 [patent_app_country] => US [patent_app_date] => 2007-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2628 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/405/07405457.pdf [firstpage_image] =>[orig_patent_app_number] => 11788440 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/788440
High temperature thermistors Apr 18, 2007 Issued
Array ( [id] => 602360 [patent_doc_number] => 07432123 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-10-07 [patent_title] => 'Methods of manufacturing high temperature thermistors' [patent_app_type] => utility [patent_app_number] => 11/788441 [patent_app_country] => US [patent_app_date] => 2007-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2635 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/432/07432123.pdf [firstpage_image] =>[orig_patent_app_number] => 11788441 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/788441
Methods of manufacturing high temperature thermistors Apr 18, 2007 Issued
Array ( [id] => 4661027 [patent_doc_number] => 20080251934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-16 [patent_title] => 'Semiconductor Device Structures and Methods of Fabricating Semiconductor Device Structures for Use in SRAM Devices' [patent_app_type] => utility [patent_app_number] => 11/734931 [patent_app_country] => US [patent_app_date] => 2007-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8930 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0251/20080251934.pdf [firstpage_image] =>[orig_patent_app_number] => 11734931 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/734931
Semiconductor Device Structures and Methods of Fabricating Semiconductor Device Structures for Use in SRAM Devices Apr 12, 2007 Abandoned
Array ( [id] => 5123515 [patent_doc_number] => 20070235785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-11 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/697641 [patent_app_country] => US [patent_app_date] => 2007-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 7513 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20070235785.pdf [firstpage_image] =>[orig_patent_app_number] => 11697641 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/697641
Semiconductor device and method of fabricating the same Apr 5, 2007 Issued
Array ( [id] => 45135 [patent_doc_number] => 07777297 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-17 [patent_title] => 'Non-planar fuse structure including angular bend' [patent_app_type] => utility [patent_app_number] => 11/693041 [patent_app_country] => US [patent_app_date] => 2007-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 4701 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/777/07777297.pdf [firstpage_image] =>[orig_patent_app_number] => 11693041 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/693041
Non-planar fuse structure including angular bend Mar 28, 2007 Issued
Array ( [id] => 4695477 [patent_doc_number] => 20080217661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'TWO-DIMENSIONAL TIME DELAY INTEGRATION VISIBLE CMOS IMAGE SENSOR' [patent_app_type] => utility [patent_app_number] => 11/683811 [patent_app_country] => US [patent_app_date] => 2007-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2878 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20080217661.pdf [firstpage_image] =>[orig_patent_app_number] => 11683811 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/683811
Two-dimensional time delay integration visible CMOS image sensor Mar 7, 2007 Issued
Array ( [id] => 5256714 [patent_doc_number] => 20070210346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'Charge transfer device' [patent_app_type] => utility [patent_app_number] => 11/714191 [patent_app_country] => US [patent_app_date] => 2007-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 17406 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20070210346.pdf [firstpage_image] =>[orig_patent_app_number] => 11714191 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/714191
Charge transfer device Mar 5, 2007 Abandoned
Array ( [id] => 5236652 [patent_doc_number] => 20070128809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-07 [patent_title] => 'METHODS OF REDUCING FLOATING BODY EFFECT' [patent_app_type] => utility [patent_app_number] => 11/673968 [patent_app_country] => US [patent_app_date] => 2007-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6104 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20070128809.pdf [firstpage_image] =>[orig_patent_app_number] => 11673968 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/673968
Methods of reducing floating body effect Feb 11, 2007 Issued
Array ( [id] => 5116814 [patent_doc_number] => 20070138528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'MEMORY STRUCTURE FOR REDUCED FLOATING BODY EFFECT' [patent_app_type] => utility [patent_app_number] => 11/673922 [patent_app_country] => US [patent_app_date] => 2007-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6085 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20070138528.pdf [firstpage_image] =>[orig_patent_app_number] => 11673922 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/673922
Memory structure for reduced floating body effect Feb 11, 2007 Issued
Array ( [id] => 311433 [patent_doc_number] => 07528465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'Integrated circuit on corrugated substrate' [patent_app_type] => utility [patent_app_number] => 11/673536 [patent_app_country] => US [patent_app_date] => 2007-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 29 [patent_no_of_words] => 11618 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/528/07528465.pdf [firstpage_image] =>[orig_patent_app_number] => 11673536 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/673536
Integrated circuit on corrugated substrate Feb 8, 2007 Issued
Array ( [id] => 583310 [patent_doc_number] => 07453090 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-18 [patent_title] => 'Semiconductor device including a semiconductor substrate formed with a shallow impurity region' [patent_app_type] => utility [patent_app_number] => 11/700849 [patent_app_country] => US [patent_app_date] => 2007-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 33 [patent_no_of_words] => 9698 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/453/07453090.pdf [firstpage_image] =>[orig_patent_app_number] => 11700849 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/700849
Semiconductor device including a semiconductor substrate formed with a shallow impurity region Jan 31, 2007 Issued
Array ( [id] => 5236631 [patent_doc_number] => 20070128788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-07 [patent_title] => 'HIGH VOLTAGE METAL OXIDE SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/669951 [patent_app_country] => US [patent_app_date] => 2007-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3913 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20070128788.pdf [firstpage_image] =>[orig_patent_app_number] => 11669951 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/669951
High voltage metal oxide semiconductor device Jan 31, 2007 Issued
Array ( [id] => 315191 [patent_doc_number] => 07525161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-28 [patent_title] => 'Strained MOS devices using source/drain epitaxy' [patent_app_type] => utility [patent_app_number] => 11/669902 [patent_app_country] => US [patent_app_date] => 2007-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4688 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/525/07525161.pdf [firstpage_image] =>[orig_patent_app_number] => 11669902 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/669902
Strained MOS devices using source/drain epitaxy Jan 30, 2007 Issued
Array ( [id] => 5076903 [patent_doc_number] => 20070120127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'Semiconductor device and semiconductor device production system' [patent_app_type] => utility [patent_app_number] => 11/698864 [patent_app_country] => US [patent_app_date] => 2007-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 24914 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20070120127.pdf [firstpage_image] =>[orig_patent_app_number] => 11698864 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/698864
Semiconductor thin film device Jan 28, 2007 Issued
Array ( [id] => 314739 [patent_doc_number] => 07524709 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-28 [patent_title] => 'Manufacturing method for a display device' [patent_app_type] => utility [patent_app_number] => 11/698862 [patent_app_country] => US [patent_app_date] => 2007-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 24 [patent_no_of_words] => 11535 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/524/07524709.pdf [firstpage_image] =>[orig_patent_app_number] => 11698862 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/698862
Manufacturing method for a display device Jan 28, 2007 Issued
Array ( [id] => 4762738 [patent_doc_number] => 20080173947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-24 [patent_title] => 'Hybrid process for forming metal gates' [patent_app_type] => utility [patent_app_number] => 11/656711 [patent_app_country] => US [patent_app_date] => 2007-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3929 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20080173947.pdf [firstpage_image] =>[orig_patent_app_number] => 11656711 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/656711
Hybrid process for forming metal gates Jan 22, 2007 Issued
Array ( [id] => 341549 [patent_doc_number] => 07501307 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-10 [patent_title] => 'Method of fabricating semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/650972 [patent_app_country] => US [patent_app_date] => 2007-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3747 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/501/07501307.pdf [firstpage_image] =>[orig_patent_app_number] => 11650972 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/650972
Method of fabricating semiconductor memory device Jan 8, 2007 Issued
Array ( [id] => 229198 [patent_doc_number] => 07602013 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-13 [patent_title] => 'Semiconductor device with recessed channel' [patent_app_type] => utility [patent_app_number] => 11/649752 [patent_app_country] => US [patent_app_date] => 2007-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 4561 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/602/07602013.pdf [firstpage_image] =>[orig_patent_app_number] => 11649752 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/649752
Semiconductor device with recessed channel Jan 4, 2007 Issued
Array ( [id] => 849104 [patent_doc_number] => 07381621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-03 [patent_title] => 'Methods of fabricating high voltage MOSFET having doped buried layer' [patent_app_type] => utility [patent_app_number] => 11/620091 [patent_app_country] => US [patent_app_date] => 2007-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 3367 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/381/07381621.pdf [firstpage_image] =>[orig_patent_app_number] => 11620091 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/620091
Methods of fabricating high voltage MOSFET having doped buried layer Jan 4, 2007 Issued
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