Jason Y. Ko

Array ( [id] => 4971428 [patent_doc_number] => 20070111430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'HIGH DENSITY MIMCAP WITH A UNIT REPEATABLE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 11/619251 [patent_app_country] => US [patent_app_date] => 2007-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3951 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20070111430.pdf [firstpage_image] =>[orig_patent_app_number] => 11619251 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 102438 [patent_doc_number] => 07723190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-25 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/647691 [patent_app_country] => US [patent_app_date] => 2006-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 2755 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/723/07723190.pdf [firstpage_image] =>[orig_patent_app_number] => 11647691 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 190858 [patent_doc_number] => 07642169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-05 [patent_title] => 'Method of making a bipolar junction transistor' [patent_app_type] => utility [patent_app_number] => 11/615741 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1893 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/642/07642169.pdf [firstpage_image] =>[orig_patent_app_number] => 11615741 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5019478 [patent_doc_number] => 20070145444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'CMOS Image Sensor and Method for Manufacturing the Same' [patent_app_type] => utility [patent_app_number] => 11/611341 [patent_app_country] => US [patent_app_date] => 2006-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3016 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20070145444.pdf [firstpage_image] =>[orig_patent_app_number] => 11611341 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 74131 [patent_doc_number] => 07749885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-06 [patent_title] => 'Semiconductor processing methods, methods of forming contact pads, and methods of forming electrical connections between metal-containing layers' [patent_app_type] => utility [patent_app_number] => 11/639771 [patent_app_country] => US [patent_app_date] => 2006-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 37 [patent_no_of_words] => 5841 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/749/07749885.pdf [firstpage_image] =>[orig_patent_app_number] => 11639771 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4782620 [patent_doc_number] => 20080135949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'Stacked silicon-germanium nanowire structure and method of forming the same' [patent_app_type] => utility [patent_app_number] => 11/636381 [patent_app_country] => US [patent_app_date] => 2006-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6089 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20080135949.pdf [firstpage_image] =>[orig_patent_app_number] => 11636381 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 191287 [patent_doc_number] => 07642600 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-01-05 [patent_title] => 'System and method for providing a low voltage thin gate input/output structure with thick gate overvoltage/backdrive protection' [patent_app_type] => utility [patent_app_number] => 11/635321 [patent_app_country] => US [patent_app_date] => 2006-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 7419 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/642/07642600.pdf [firstpage_image] =>[orig_patent_app_number] => 11635321 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5116816 [patent_doc_number] => 20070138530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Electrically floating body memory cell and array, and method of operating or controlling same' [patent_app_type] => utility [patent_app_number] => 11/633311 [patent_app_country] => US [patent_app_date] => 2006-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9746 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20070138530.pdf [firstpage_image] =>[orig_patent_app_number] => 11633311 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 160073 [patent_doc_number] => 07675097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-09 [patent_title] => 'Silicide strapping in imager transfer gate device' [patent_app_type] => utility [patent_app_number] => 11/565801 [patent_app_country] => US [patent_app_date] => 2006-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 6033 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/675/07675097.pdf [firstpage_image] =>[orig_patent_app_number] => 11565801 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4820524 [patent_doc_number] => 20080121882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'Method to reduce junction leakage through partial regrowth with ultrafast anneal and structures formed thereby' [patent_app_type] => utility [patent_app_number] => 11/594301 [patent_app_country] => US [patent_app_date] => 2006-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3452 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20080121882.pdf [firstpage_image] =>[orig_patent_app_number] => 11594301 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 221352 [patent_doc_number] => 07608898 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-27 [patent_title] => 'One transistor DRAM cell structure' [patent_app_type] => utility [patent_app_number] => 11/554851 [patent_app_country] => US [patent_app_date] => 2006-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 5379 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/608/07608898.pdf [firstpage_image] =>[orig_patent_app_number] => 11554851 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 363847 [patent_doc_number] => 07482662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-27 [patent_title] => 'High voltage semiconductor device utilizing a deep trench structure' [patent_app_type] => utility [patent_app_number] => 11/554368 [patent_app_country] => US [patent_app_date] => 2006-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2697 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/482/07482662.pdf [firstpage_image] =>[orig_patent_app_number] => 11554368 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 585087 [patent_doc_number] => 07442613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'Methods of forming an asymmetric field effect transistor' [patent_app_type] => utility [patent_app_number] => 11/586359 [patent_app_country] => US [patent_app_date] => 2006-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 5545 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/442/07442613.pdf [firstpage_image] =>[orig_patent_app_number] => 11586359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5213611 [patent_doc_number] => 20070102691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Silver-selenide/chalcogenide glass stack for resistance variable memory' [patent_app_type] => utility [patent_app_number] => 11/585259 [patent_app_country] => US [patent_app_date] => 2006-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4867 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20070102691.pdf [firstpage_image] =>[orig_patent_app_number] => 11585259 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4913083 [patent_doc_number] => 20080093682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'Polysilicon levels for silicided structures including MOSFET gate electrodes and 3D devices' [patent_app_type] => utility [patent_app_number] => 11/583491 [patent_app_country] => US [patent_app_date] => 2006-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5036 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20080093682.pdf [firstpage_image] =>[orig_patent_app_number] => 11583491 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 45080 [patent_doc_number] => 07777268 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-17 [patent_title] => 'Dual-gate device' [patent_app_type] => utility [patent_app_number] => 11/548231 [patent_app_country] => US [patent_app_date] => 2006-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 27 [patent_no_of_words] => 9082 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/777/07777268.pdf [firstpage_image] =>[orig_patent_app_number] => 11548231 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 349181 [patent_doc_number] => 07495299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-24 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/544611 [patent_app_country] => US [patent_app_date] => 2006-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 22 [patent_no_of_words] => 7308 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/495/07495299.pdf [firstpage_image] =>[orig_patent_app_number] => 11544611 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 482545 [patent_doc_number] => 07220629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-22 [patent_title] => 'Method of manufacturing an integrated circuit with multilength power transistor elements' [patent_app_type] => utility [patent_app_number] => 11/540261 [patent_app_country] => US [patent_app_date] => 2006-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3291 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/220/07220629.pdf [firstpage_image] =>[orig_patent_app_number] => 11540261 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5168849 [patent_doc_number] => 20070069280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/528592 [patent_app_country] => US [patent_app_date] => 2006-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2486 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20070069280.pdf [firstpage_image] =>[orig_patent_app_number] => 11528592 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 197540 [patent_doc_number] => 07638845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-29 [patent_title] => 'Semiconductor device with buried conductive layer' [patent_app_type] => utility [patent_app_number] => 11/535741 [patent_app_country] => US [patent_app_date] => 2006-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 78 [patent_no_of_words] => 13115 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/638/07638845.pdf [firstpage_image] =>[orig_patent_app_number] => 11535741 [rel_patent_id] =>[rel_patent_doc_number] =>)