Jason Y. Ko

Array ( [id] => 4723921 [patent_doc_number] => 20080203462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'Finfet-Based Non-Volatile Memory Device' [patent_app_type] => utility [patent_app_number] => 12/067992 [patent_app_country] => US [patent_app_date] => 2006-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3715 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20080203462.pdf [firstpage_image] =>[orig_patent_app_number] => 12067992 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 307795 [patent_doc_number] => 07531868 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-12 [patent_title] => 'Non-volatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/523801 [patent_app_country] => US [patent_app_date] => 2006-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 13973 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/531/07531868.pdf [firstpage_image] =>[orig_patent_app_number] => 11523801 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5104363 [patent_doc_number] => 20070063238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-22 [patent_title] => 'Semiconductor memory and driving method for the same' [patent_app_type] => utility [patent_app_number] => 11/520011 [patent_app_country] => US [patent_app_date] => 2006-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14943 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20070063238.pdf [firstpage_image] =>[orig_patent_app_number] => 11520011 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4992223 [patent_doc_number] => 20070007567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'Semiconductor substrate and production process thereof' [patent_app_type] => utility [patent_app_number] => 11/518891 [patent_app_country] => US [patent_app_date] => 2006-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10536 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20070007567.pdf [firstpage_image] =>[orig_patent_app_number] => 11518891 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 253023 [patent_doc_number] => 07579657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-25 [patent_title] => 'Semiconductor device with multiple channels' [patent_app_type] => utility [patent_app_number] => 11/517211 [patent_app_country] => US [patent_app_date] => 2006-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 30 [patent_no_of_words] => 5273 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/579/07579657.pdf [firstpage_image] =>[orig_patent_app_number] => 11517211 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 425067 [patent_doc_number] => 07271049 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-18 [patent_title] => 'Method of forming self-aligned low-k gate cap' [patent_app_type] => utility [patent_app_number] => 11/514605 [patent_app_country] => US [patent_app_date] => 2006-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 6111 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/271/07271049.pdf [firstpage_image] =>[orig_patent_app_number] => 11514605 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5145647 [patent_doc_number] => 20070045701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Storage node, method of fabricating the same, semiconductor device and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/508931 [patent_app_country] => US [patent_app_date] => 2006-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4104 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20070045701.pdf [firstpage_image] =>[orig_patent_app_number] => 11508931 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7595218 [patent_doc_number] => 07626243 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-01 [patent_title] => 'ESD protection for bipolar-CMOS-DMOS integrated circuit devices' [patent_app_type] => utility [patent_app_number] => 11/499381 [patent_app_country] => US [patent_app_date] => 2006-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 4723 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/626/07626243.pdf [firstpage_image] =>[orig_patent_app_number] => 11499381 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4654891 [patent_doc_number] => 20080023751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'INTEGRATED CIRCUIT MEMORY SYSTEM EMPLOYING SILICON RICH LAYERS' [patent_app_type] => utility [patent_app_number] => 11/461131 [patent_app_country] => US [patent_app_date] => 2006-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4047 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20080023751.pdf [firstpage_image] =>[orig_patent_app_number] => 11461131 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4657662 [patent_doc_number] => 20080026523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'Structure and method to implement dual stressor layers with improved silicide control' [patent_app_type] => utility [patent_app_number] => 11/495508 [patent_app_country] => US [patent_app_date] => 2006-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3655 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20080026523.pdf [firstpage_image] =>[orig_patent_app_number] => 11495508 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5732996 [patent_doc_number] => 20060258113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'CAPACITOR STRUCTURE' [patent_app_type] => utility [patent_app_number] => 11/460021 [patent_app_country] => US [patent_app_date] => 2006-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3944 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20060258113.pdf [firstpage_image] =>[orig_patent_app_number] => 11460021 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 239910 [patent_doc_number] => 07592628 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-22 [patent_title] => 'Display with thin film transistor devices having different electrical characteristics in pixel and driving regions' [patent_app_type] => utility [patent_app_number] => 11/490551 [patent_app_country] => US [patent_app_date] => 2006-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3942 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/592/07592628.pdf [firstpage_image] =>[orig_patent_app_number] => 11490551 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4908405 [patent_doc_number] => 20080019171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-24 [patent_title] => 'Dual port memory device with reduced coupling effect' [patent_app_type] => utility [patent_app_number] => 11/488501 [patent_app_country] => US [patent_app_date] => 2006-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2627 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20080019171.pdf [firstpage_image] =>[orig_patent_app_number] => 11488501 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 195840 [patent_doc_number] => 07635623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-22 [patent_title] => 'Methods of forming capacitors' [patent_app_type] => utility [patent_app_number] => 11/488587 [patent_app_country] => US [patent_app_date] => 2006-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5376 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/635/07635623.pdf [firstpage_image] =>[orig_patent_app_number] => 11488587 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4800492 [patent_doc_number] => 20080012079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'Memory cell having active region sized for low reset current and method of fabricating such memory cells' [patent_app_type] => utility [patent_app_number] => 11/487876 [patent_app_country] => US [patent_app_date] => 2006-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7605 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20080012079.pdf [firstpage_image] =>[orig_patent_app_number] => 11487876 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 315203 [patent_doc_number] => 07525173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-28 [patent_title] => 'Layout structure of MOS transistors on an active region' [patent_app_type] => utility [patent_app_number] => 11/485341 [patent_app_country] => US [patent_app_date] => 2006-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4853 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/525/07525173.pdf [firstpage_image] =>[orig_patent_app_number] => 11485341 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 203353 [patent_doc_number] => 07633101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-15 [patent_title] => 'Oxide isolated metal silicon-gate JFET' [patent_app_type] => utility [patent_app_number] => 11/484402 [patent_app_country] => US [patent_app_date] => 2006-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 7003 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/633/07633101.pdf [firstpage_image] =>[orig_patent_app_number] => 11484402 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5152013 [patent_doc_number] => 20070034895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-15 [patent_title] => 'Folded-gate MOS transistor' [patent_app_type] => utility [patent_app_number] => 11/482531 [patent_app_country] => US [patent_app_date] => 2006-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4226 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20070034895.pdf [firstpage_image] =>[orig_patent_app_number] => 11482531 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4930478 [patent_doc_number] => 20080001253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'LOW INDUCTANCE CAPACITORS, METHODS OF ASSEMBLING SAME, AND SYSTEMS CONTAINING SAME' [patent_app_type] => utility [patent_app_number] => 11/428331 [patent_app_country] => US [patent_app_date] => 2006-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6667 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20080001253.pdf [firstpage_image] =>[orig_patent_app_number] => 11428331 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1076931 [patent_doc_number] => 07615444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-10 [patent_title] => 'Method for forming a capacitor structure' [patent_app_type] => utility [patent_app_number] => 11/477581 [patent_app_country] => US [patent_app_date] => 2006-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 3018 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/615/07615444.pdf [firstpage_image] =>[orig_patent_app_number] => 11477581 [rel_patent_id] =>[rel_patent_doc_number] =>)