Jason Y. Ko

Array ( [id] => 6285818 [patent_doc_number] => 20100237321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/793172 [patent_app_country] => US [patent_app_date] => 2010-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9017 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20100237321.pdf [firstpage_image] =>[orig_patent_app_number] => 12793172 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7555359 [patent_doc_number] => 08067260 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-11-29 [patent_title] => 'Fabricating sub-lithographic contacts' [patent_app_type] => utility [patent_app_number] => 12/792992 [patent_app_country] => US [patent_app_date] => 2010-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2230 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/067/08067260.pdf [firstpage_image] =>[orig_patent_app_number] => 12792992 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6519390 [patent_doc_number] => 20100230819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-16 [patent_title] => 'Semiconductor Constructions' [patent_app_type] => utility [patent_app_number] => 12/785263 [patent_app_country] => US [patent_app_date] => 2010-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 5841 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20100230819.pdf [firstpage_image] =>[orig_patent_app_number] => 12785263 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8282803 [patent_doc_number] => 08216905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-10 [patent_title] => 'Stress engineering to reduce dark current of CMOS image sensors' [patent_app_type] => utility [patent_app_number] => 12/768063 [patent_app_country] => US [patent_app_date] => 2010-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5048 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12768063 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9762993 [patent_doc_number] => 08847321 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-30 [patent_title] => 'Cascode CMOS structure' [patent_app_type] => utility [patent_app_number] => 12/766972 [patent_app_country] => US [patent_app_date] => 2010-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2847 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12766972 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7496807 [patent_doc_number] => 20110260247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'LDMOS TRANSISTORS WITH A SPLIT GATE' [patent_app_type] => utility [patent_app_number] => 12/767536 [patent_app_country] => US [patent_app_date] => 2010-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3679 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20110260247.pdf [firstpage_image] =>[orig_patent_app_number] => 12767536 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8772881 [patent_doc_number] => 08426839 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-04-23 [patent_title] => 'Conducting bridge random access memory (CBRAM) device structures' [patent_app_type] => utility [patent_app_number] => 12/767552 [patent_app_country] => US [patent_app_date] => 2010-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 71 [patent_no_of_words] => 11220 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12767552 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8630468 [patent_doc_number] => 08362541 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-29 [patent_title] => 'Manufacturing method of dynamic random access memory' [patent_app_type] => utility [patent_app_number] => 12/765873 [patent_app_country] => US [patent_app_date] => 2010-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5737 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12765873 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8943997 [patent_doc_number] => 08497175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-30 [patent_title] => 'Method of fabricating FinFET devices' [patent_app_type] => utility [patent_app_number] => 12/766055 [patent_app_country] => US [patent_app_date] => 2010-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 44 [patent_no_of_words] => 7539 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12766055 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7496812 [patent_doc_number] => 20110260252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'USE OF EPITAXIAL NI SILICIDE' [patent_app_type] => utility [patent_app_number] => 12/766468 [patent_app_country] => US [patent_app_date] => 2010-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3278 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20110260252.pdf [firstpage_image] =>[orig_patent_app_number] => 12766468 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6470641 [patent_doc_number] => 20100207188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-19 [patent_title] => 'Semiconductor device and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 12/662590 [patent_app_country] => US [patent_app_date] => 2010-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3309 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20100207188.pdf [firstpage_image] =>[orig_patent_app_number] => 12662590 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7496805 [patent_doc_number] => 20110260245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'Cost Effective Global Isolation and Power Dissipation For Power Integrated Circuit Device' [patent_app_type] => utility [patent_app_number] => 12/766454 [patent_app_country] => US [patent_app_date] => 2010-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5002 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20110260245.pdf [firstpage_image] =>[orig_patent_app_number] => 12766454 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8555774 [patent_doc_number] => 08330249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-11 [patent_title] => 'Semiconductor device with driver circuit and memory element' [patent_app_type] => utility [patent_app_number] => 12/754928 [patent_app_country] => US [patent_app_date] => 2010-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 36 [patent_no_of_words] => 17182 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12754928 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6444897 [patent_doc_number] => 20100188901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-29 [patent_title] => 'Three-Terminal Single Poly NMOS Non-Volatile Memory Cell' [patent_app_type] => utility [patent_app_number] => 12/730186 [patent_app_country] => US [patent_app_date] => 2010-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10607 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20100188901.pdf [firstpage_image] =>[orig_patent_app_number] => 12730186 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6618224 [patent_doc_number] => 20100172184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-08 [patent_title] => 'Asymmetric Single Poly NMOS Non-Volatile Memory Cell' [patent_app_type] => utility [patent_app_number] => 12/730176 [patent_app_country] => US [patent_app_date] => 2010-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8789 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20100172184.pdf [firstpage_image] =>[orig_patent_app_number] => 12730176 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6230491 [patent_doc_number] => 20100184266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-22 [patent_title] => ' METHOD OF MANUFACTURING A NON-VOLATILE NAND MEMORY SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/715455 [patent_app_country] => US [patent_app_date] => 2010-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 14994 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20100184266.pdf [firstpage_image] =>[orig_patent_app_number] => 12715455 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8178195 [patent_doc_number] => 08178916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-15 [patent_title] => 'Nonvolatile semiconductor storage device' [patent_app_type] => utility [patent_app_number] => 12/711512 [patent_app_country] => US [patent_app_date] => 2010-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 6777 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/178/08178916.pdf [firstpage_image] =>[orig_patent_app_number] => 12711512 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7800944 [patent_doc_number] => 08129214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-06 [patent_title] => 'Phase change memory devices having dual lower electrodes and methods of fabricating the same' [patent_app_type] => utility [patent_app_number] => 12/709536 [patent_app_country] => US [patent_app_date] => 2010-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7674 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/129/08129214.pdf [firstpage_image] =>[orig_patent_app_number] => 12709536 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6418881 [patent_doc_number] => 20100167450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'Solid-state imaging element and method for producing the same' [patent_app_type] => utility [patent_app_number] => 12/656925 [patent_app_country] => US [patent_app_date] => 2010-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5581 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20100167450.pdf [firstpage_image] =>[orig_patent_app_number] => 12656925 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6470769 [patent_doc_number] => 20100207199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-19 [patent_title] => 'SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 12/704000 [patent_app_country] => US [patent_app_date] => 2010-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 16904 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20100207199.pdf [firstpage_image] =>[orig_patent_app_number] => 12704000 [rel_patent_id] =>[rel_patent_doc_number] =>)