Search

Jason Y. Ko

Examiner (ID: 1948)

Most Active Art Unit
1711
Art Unit(s)
1792, 1711
Total Applications
1498
Issued Applications
1154
Pending Applications
89
Abandoned Applications
287

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6494398 [patent_doc_number] => 20100200913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'SEMICONDUCTOR STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 12/703968 [patent_app_country] => US [patent_app_date] => 2010-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 8032 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20100200913.pdf [firstpage_image] =>[orig_patent_app_number] => 12703968 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/703968
Semiconductor surround gate SRAM storage device Feb 10, 2010 Issued
Array ( [id] => 8114513 [patent_doc_number] => 08158468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-17 [patent_title] => 'Production method for surrounding gate transistor semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/703991 [patent_app_country] => US [patent_app_date] => 2010-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 17043 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/158/08158468.pdf [firstpage_image] =>[orig_patent_app_number] => 12703991 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/703991
Production method for surrounding gate transistor semiconductor device Feb 10, 2010 Issued
Array ( [id] => 8270796 [patent_doc_number] => 08212298 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-03 [patent_title] => 'Semiconductor storage device and methods of producing it' [patent_app_type] => utility [patent_app_number] => 12/704239 [patent_app_country] => US [patent_app_date] => 2010-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 36 [patent_no_of_words] => 12950 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 408 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12704239 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/704239
Semiconductor storage device and methods of producing it Feb 10, 2010 Issued
Array ( [id] => 8114483 [patent_doc_number] => 08158453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-17 [patent_title] => 'Methods of forming silicide strapping in imager transfer gate device' [patent_app_type] => utility [patent_app_number] => 12/699419 [patent_app_country] => US [patent_app_date] => 2010-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 6069 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/158/08158453.pdf [firstpage_image] =>[orig_patent_app_number] => 12699419 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/699419
Methods of forming silicide strapping in imager transfer gate device Feb 2, 2010 Issued
Array ( [id] => 8165556 [patent_doc_number] => 08173990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-08 [patent_title] => 'Memory array with a selector connected to multiple resistive cells' [patent_app_type] => utility [patent_app_number] => 12/691549 [patent_app_country] => US [patent_app_date] => 2010-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3336 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/173/08173990.pdf [firstpage_image] =>[orig_patent_app_number] => 12691549 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/691549
Memory array with a selector connected to multiple resistive cells Jan 20, 2010 Issued
Array ( [id] => 9087780 [patent_doc_number] => 08559214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-15 [patent_title] => 'Magnetic memory device and magnetic random access memory' [patent_app_type] => utility [patent_app_number] => 13/139604 [patent_app_country] => US [patent_app_date] => 2009-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 101 [patent_no_of_words] => 47098 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13139604 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/139604
Magnetic memory device and magnetic random access memory Dec 23, 2009 Issued
Array ( [id] => 6408785 [patent_doc_number] => 20100140579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'SILVER-SELENIDE/CHALCOGENIDE GLASS STACK FOR RESISTANCE VARIABLE MEMORY' [patent_app_type] => utility [patent_app_number] => 12/630700 [patent_app_country] => US [patent_app_date] => 2009-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4948 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20100140579.pdf [firstpage_image] =>[orig_patent_app_number] => 12630700 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/630700
Silver-selenide/chalcogenide glass stack for resistance variable memory Dec 2, 2009 Issued
Array ( [id] => 10502696 [patent_doc_number] => 09231099 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-05 [patent_title] => 'Semiconductor power MOSFET device having a super-junction drift region' [patent_app_type] => utility [patent_app_number] => 13/140316 [patent_app_country] => US [patent_app_date] => 2009-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4747 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 420 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13140316 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/140316
Semiconductor power MOSFET device having a super-junction drift region Nov 26, 2009 Issued
Array ( [id] => 10112040 [patent_doc_number] => 09147459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-29 [patent_title] => 'Dynamic random access memories with an increased stability of the MOS memory cells' [patent_app_type] => utility [patent_app_number] => 12/610895 [patent_app_country] => US [patent_app_date] => 2009-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5405 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12610895 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/610895
Dynamic random access memories with an increased stability of the MOS memory cells Nov 1, 2009 Issued
Array ( [id] => 6545293 [patent_doc_number] => 20100044812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'STRATIFIED PHOTODIODE FOR HIGH RESOLUTION CMOS IMAGE SENSOR IMPLEMENTED WITH STI TECHNOLOGY' [patent_app_type] => utility [patent_app_number] => 12/608734 [patent_app_country] => US [patent_app_date] => 2009-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3474 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20100044812.pdf [firstpage_image] =>[orig_patent_app_number] => 12608734 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/608734
Stratified photodiode for high resolution CMOS image sensor implemented with STI technology Oct 28, 2009 Issued
Array ( [id] => 6545448 [patent_doc_number] => 20100044824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'STRATIFIED PHOTODIODE FOR HIGH RESOLUTION CMOS IMAGE SENSOR IMPLEMENTED WITH STI TECHNOLOGY' [patent_app_type] => utility [patent_app_number] => 12/608731 [patent_app_country] => US [patent_app_date] => 2009-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3474 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20100044824.pdf [firstpage_image] =>[orig_patent_app_number] => 12608731 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/608731
Stratified photodiode for high resolution CMOS image sensor implemented with STI technology Oct 28, 2009 Issued
Array ( [id] => 6249718 [patent_doc_number] => 20100027346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-04 [patent_title] => 'Asymmetric Single Poly NMOS Non-Volatile Memory Cell' [patent_app_type] => utility [patent_app_number] => 12/582627 [patent_app_country] => US [patent_app_date] => 2009-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8764 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20100027346.pdf [firstpage_image] =>[orig_patent_app_number] => 12582627 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/582627
Asymmetric Single Poly NMOS Non-Volatile Memory Cell Oct 19, 2009 Abandoned
Array ( [id] => 6249719 [patent_doc_number] => 20100027347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-04 [patent_title] => 'Three-Terminal Single Poly NMOS Non-Volatile Memory Cell' [patent_app_type] => utility [patent_app_number] => 12/582646 [patent_app_country] => US [patent_app_date] => 2009-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10604 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20100027347.pdf [firstpage_image] =>[orig_patent_app_number] => 12582646 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/582646
Three-Terminal Single Poly NMOS Non-Volatile Memory Cell Oct 19, 2009 Abandoned
Array ( [id] => 6537907 [patent_doc_number] => 20100015757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-21 [patent_title] => 'BRIDGE RESISTANCE RANDOM ACCESS MEMORY DEVICE AND METHOD WITH A SINGULAR CONTACT STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/558401 [patent_app_country] => US [patent_app_date] => 2009-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6543 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20100015757.pdf [firstpage_image] =>[orig_patent_app_number] => 12558401 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/558401
Bridge resistance random access memory device and method with a singular contact structure Oct 1, 2009 Issued
Array ( [id] => 8176987 [patent_doc_number] => 08178407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-15 [patent_title] => 'Systems and methods for a high density, compact memory array' [patent_app_type] => utility [patent_app_number] => 12/561395 [patent_app_country] => US [patent_app_date] => 2009-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4400 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/178/08178407.pdf [firstpage_image] =>[orig_patent_app_number] => 12561395 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/561395
Systems and methods for a high density, compact memory array Sep 16, 2009 Issued
Array ( [id] => 8435475 [patent_doc_number] => 08283244 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-09 [patent_title] => 'Method for forming one transistor DRAM cell structure' [patent_app_type] => utility [patent_app_number] => 12/558284 [patent_app_country] => US [patent_app_date] => 2009-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 5379 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12558284 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/558284
Method for forming one transistor DRAM cell structure Sep 10, 2009 Issued
Array ( [id] => 10858134 [patent_doc_number] => 08884338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-11 [patent_title] => 'Semiconductor integrated-circuit device with standard cells' [patent_app_type] => utility [patent_app_number] => 12/557995 [patent_app_country] => US [patent_app_date] => 2009-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2770 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12557995 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/557995
Semiconductor integrated-circuit device with standard cells Sep 10, 2009 Issued
Array ( [id] => 6518545 [patent_doc_number] => 20100123175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-20 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/557422 [patent_app_country] => US [patent_app_date] => 2009-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5318 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20100123175.pdf [firstpage_image] =>[orig_patent_app_number] => 12557422 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/557422
SEMICONDUCTOR DEVICE Sep 9, 2009 Abandoned
Array ( [id] => 6562318 [patent_doc_number] => 20100059805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/556648 [patent_app_country] => US [patent_app_date] => 2009-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9356 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20100059805.pdf [firstpage_image] =>[orig_patent_app_number] => 12556648 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/556648
DRAM semiconductor device with pad electrode Sep 9, 2009 Issued
Array ( [id] => 6004063 [patent_doc_number] => 20110057266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-10 [patent_title] => 'BIPOLAR TRANSISTOR INTEGRATED WITH METAL GATE CMOS DEVICES' [patent_app_type] => utility [patent_app_number] => 12/556205 [patent_app_country] => US [patent_app_date] => 2009-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8031 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20110057266.pdf [firstpage_image] =>[orig_patent_app_number] => 12556205 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/556205
Method of forming bipolar transistor integrated with metal gate CMOS devices Sep 8, 2009 Issued
Menu