Javaid H Nasri

Array ( [id] => 18906767 [patent_doc_number] => 20240022252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => LEVEL SHIFTING CIRCUIT MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 18/447154 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15619 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447154 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18790172 [patent_doc_number] => 20230378957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => LEVEL CONVERTER CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/364950 [patent_app_country] => US [patent_app_date] => 2023-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3049 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18364950 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19329384 [patent_doc_number] => 12047079 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Flip-flop circuit and method [patent_app_type] => utility [patent_app_number] => 18/302178 [patent_app_country] => US [patent_app_date] => 2023-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 12477 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18302178 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18488051 [patent_doc_number] => 20230215397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => Driver Circuit, Display Device, And Electronic Device [patent_app_type] => utility [patent_app_number] => 18/120489 [patent_app_country] => US [patent_app_date] => 2023-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 35442 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18120489 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18424721 [patent_doc_number] => 20230179186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => SENSE AMPLIFIER FOR COUPLING EFFECT REDUCTION [patent_app_type] => utility [patent_app_number] => 18/163461 [patent_app_country] => US [patent_app_date] => 2023-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13180 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18163461 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18981831 [patent_doc_number] => 11907003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Output signal generation circuit [patent_app_type] => utility [patent_app_number] => 18/156148 [patent_app_country] => US [patent_app_date] => 2023-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5619 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18156148 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18735533 [patent_doc_number] => 11804274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-31 [patent_title] => Shift register circuit, active matrix substrate, and display apparatus [patent_app_type] => utility [patent_app_number] => 18/097173 [patent_app_country] => US [patent_app_date] => 2023-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 24 [patent_no_of_words] => 10571 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 500 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18097173 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18680921 [patent_doc_number] => 20230318584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => MULTI-BIT FLIP-FLOP CIRCUIT WITH REDUCED AREA AND REDUCED WIRE COMPLEXITY [patent_app_type] => utility [patent_app_number] => 18/092507 [patent_app_country] => US [patent_app_date] => 2023-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13726 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18092507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18875364 [patent_doc_number] => 11863190 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-01-02 [patent_title] => Multi-bit flip-flops utilizing shared clock elements [patent_app_type] => utility [patent_app_number] => 18/091694 [patent_app_country] => US [patent_app_date] => 2022-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 23891 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18091694 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18474134 [patent_doc_number] => 20230208422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => LEVEL SHIFTER ENABLE [patent_app_type] => utility [patent_app_number] => 18/146282 [patent_app_country] => US [patent_app_date] => 2022-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5170 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18146282 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18501121 [patent_doc_number] => 20230223937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => MULTI-BIT LEVEL SHIFTER WITH SHARED ENABLE SIGNALS [patent_app_type] => utility [patent_app_number] => 18/063731 [patent_app_country] => US [patent_app_date] => 2022-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7994 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18063731 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18319725 [patent_doc_number] => 20230117853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => CIRCUIT AND METHOD FOR EXPANDING LOCK RANGE OF INJECTION-LOCKED OSCILLATORS [patent_app_type] => utility [patent_app_number] => 18/076359 [patent_app_country] => US [patent_app_date] => 2022-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2222 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18076359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19168974 [patent_doc_number] => 11984893 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Data retention circuit and method [patent_app_type] => utility [patent_app_number] => 17/994227 [patent_app_country] => US [patent_app_date] => 2022-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3191 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17994227 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18424722 [patent_doc_number] => 20230179187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => Semiconductor devices and multi-bit flip-flop circuits having an asymmetrical row structure [patent_app_type] => utility [patent_app_number] => 17/989654 [patent_app_country] => US [patent_app_date] => 2022-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7196 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17989654 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18272014 [patent_doc_number] => 20230093256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/988841 [patent_app_country] => US [patent_app_date] => 2022-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 54357 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17988841 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18805226 [patent_doc_number] => 11838398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-05 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 18/051138 [patent_app_country] => US [patent_app_date] => 2022-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 15946 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18051138 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18464890 [patent_doc_number] => 11689190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => D flip-flop [patent_app_type] => utility [patent_app_number] => 17/973740 [patent_app_country] => US [patent_app_date] => 2022-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 34 [patent_no_of_words] => 10009 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 623 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17973740 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18352384 [patent_doc_number] => 20230140495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => CLOCK SIGNAL GENERATION CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/968791 [patent_app_country] => US [patent_app_date] => 2022-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2617 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17968791 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18139315 [patent_doc_number] => 20230013151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => CLOCK CIRCUIT IN A PROCESSOR INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/947699 [patent_app_country] => US [patent_app_date] => 2022-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11348 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17947699 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19230171 [patent_doc_number] => 12009816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Level-conversion circuits for signaling across voltage domains [patent_app_type] => utility [patent_app_number] => 17/932052 [patent_app_country] => US [patent_app_date] => 2022-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 35 [patent_no_of_words] => 6247 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17932052 [rel_patent_id] =>[rel_patent_doc_number] =>)