Search

Javaid H. Nasri

Examiner (ID: 5819, Phone: (571)272-2095 , Office: P/2831 )

Most Active Art Unit
2839
Art Unit(s)
2839, 2831, 2833
Total Applications
2279
Issued Applications
1981
Pending Applications
35
Abandoned Applications
269

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18609932 [patent_doc_number] => 11751431 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Display apparatus and electronic device including the same [patent_app_type] => utility [patent_app_number] => 17/323161 [patent_app_country] => US [patent_app_date] => 2021-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11903 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17323161 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/323161
Display apparatus and electronic device including the same May 17, 2021 Issued
Array ( [id] => 17070835 [patent_doc_number] => 20210273052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => BIPOLAR-TRANSISTOR DEVICE AND CORRESPONDING FABRICATION PROCESS [patent_app_type] => utility [patent_app_number] => 17/323170 [patent_app_country] => US [patent_app_date] => 2021-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4452 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17323170 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/323170
Bipolar-transistor device and corresponding fabrication process May 17, 2021 Issued
Array ( [id] => 17509177 [patent_doc_number] => 20220102280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => Very Fine Pitch and Wiring Density Organic Side by Side Chiplet Integration [patent_app_type] => utility [patent_app_number] => 17/321080 [patent_app_country] => US [patent_app_date] => 2021-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7266 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17321080 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/321080
Very fine pitch and wiring density organic side by side chiplet integration May 13, 2021 Issued
Array ( [id] => 18494247 [patent_doc_number] => 11699668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-11 [patent_title] => Semiconductor device package having warpage control and method of forming the same [patent_app_type] => utility [patent_app_number] => 17/318139 [patent_app_country] => US [patent_app_date] => 2021-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 7400 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17318139 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/318139
Semiconductor device package having warpage control and method of forming the same May 11, 2021 Issued
Array ( [id] => 18088668 [patent_doc_number] => 11538807 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-27 [patent_title] => Method for fabricating a semiconductor device including a gate structure with an inclined side wall [patent_app_type] => utility [patent_app_number] => 17/318133 [patent_app_country] => US [patent_app_date] => 2021-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 31 [patent_no_of_words] => 11048 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17318133 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/318133
Method for fabricating a semiconductor device including a gate structure with an inclined side wall May 11, 2021 Issued
Array ( [id] => 18704710 [patent_doc_number] => 11791227 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Electronic device package [patent_app_type] => utility [patent_app_number] => 17/317770 [patent_app_country] => US [patent_app_date] => 2021-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 26 [patent_no_of_words] => 7092 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17317770 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/317770
Electronic device package May 10, 2021 Issued
Array ( [id] => 17993193 [patent_doc_number] => 20220359230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => ENCAPSULATION WARPAGE REDUCTION FOR SEMICONDUCTOR DIE ASSEMBLIES AND ASSOCIATED METHODS AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/315588 [patent_app_country] => US [patent_app_date] => 2021-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8548 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17315588 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/315588
Encapsulation warpage reduction for semiconductor die assemblies and associated methods and systems May 9, 2021 Issued
Array ( [id] => 18219542 [patent_doc_number] => 11594491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Multi-die interconnect [patent_app_type] => utility [patent_app_number] => 17/245903 [patent_app_country] => US [patent_app_date] => 2021-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 10073 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17245903 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/245903
Multi-die interconnect Apr 29, 2021 Issued
Array ( [id] => 20216146 [patent_doc_number] => 12412800 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Integrated circuit package having enhanced thermal dissipation structure [patent_app_type] => utility [patent_app_number] => 17/239776 [patent_app_country] => US [patent_app_date] => 2021-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17239776 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/239776
Integrated circuit package having enhanced thermal dissipation structure Apr 25, 2021 Issued
Array ( [id] => 17963649 [patent_doc_number] => 20220344230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/239478 [patent_app_country] => US [patent_app_date] => 2021-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7352 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17239478 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/239478
Semiconductor device package Apr 22, 2021 Issued
Array ( [id] => 17010974 [patent_doc_number] => 20210242135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => DISPLAY DEVICES AND METHODS FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/237154 [patent_app_country] => US [patent_app_date] => 2021-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8480 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17237154 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/237154
DISPLAY DEVICES AND METHODS FOR MANUFACTURING THE SAME Apr 21, 2021 Abandoned
Array ( [id] => 18464442 [patent_doc_number] => 11688738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Composite transistor with electrodes extending to active regions [patent_app_type] => utility [patent_app_number] => 17/233753 [patent_app_country] => US [patent_app_date] => 2021-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 60 [patent_no_of_words] => 15227 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17233753 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/233753
Composite transistor with electrodes extending to active regions Apr 18, 2021 Issued
Array ( [id] => 17855212 [patent_doc_number] => 20220285255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => WIRING BOARD WITH EMBEDDED INTERPOSER SUBSTRATE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/232109 [patent_app_country] => US [patent_app_date] => 2021-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4682 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17232109 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/232109
Wiring board with interposer substrate surrounded by underfill and embedded in main substrate and method of fabricating the same Apr 14, 2021 Issued
Array ( [id] => 18349811 [patent_doc_number] => 20230137922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => ARRAY SUBSTRATE, MANUFACTURING PROCESS OF ARRAY SUBSTRATE, AND DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 17/287169 [patent_app_country] => US [patent_app_date] => 2021-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8131 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17287169 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/287169
Array substrate including photosensitive element and display panel Apr 13, 2021 Issued
Array ( [id] => 18387321 [patent_doc_number] => 11658114 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Fusible structures and methods of manufacturing same [patent_app_type] => utility [patent_app_number] => 17/229345 [patent_app_country] => US [patent_app_date] => 2021-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 9520 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17229345 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/229345
Fusible structures and methods of manufacturing same Apr 12, 2021 Issued
Array ( [id] => 20436053 [patent_doc_number] => 12507582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-23 [patent_title] => Perovskite displays and methods of formation [patent_app_type] => utility [patent_app_number] => 17/915819 [patent_app_country] => US [patent_app_date] => 2021-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17915819 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/915819
Perovskite displays and methods of formation Mar 31, 2021 Issued
Array ( [id] => 17551556 [patent_doc_number] => 20220122898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => INTEGRATED FAN OUT PACKAGE AND METHOD [patent_app_type] => utility [patent_app_number] => 17/220722 [patent_app_country] => US [patent_app_date] => 2021-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19685 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17220722 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/220722
Integrated fan out method utilizing a filler-free insulating material Mar 31, 2021 Issued
Array ( [id] => 19371695 [patent_doc_number] => 12063800 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Photoelectric conversion element that reduces a residual image while enhancing heat resistance [patent_app_type] => utility [patent_app_number] => 17/220747 [patent_app_country] => US [patent_app_date] => 2021-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 10057 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17220747 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/220747
Photoelectric conversion element that reduces a residual image while enhancing heat resistance Mar 31, 2021 Issued
Array ( [id] => 19031215 [patent_doc_number] => 11930590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Stress relief for flip-chip packaged devices [patent_app_type] => utility [patent_app_number] => 17/218792 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 7189 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17218792 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/218792
Stress relief for flip-chip packaged devices Mar 30, 2021 Issued
Array ( [id] => 16966112 [patent_doc_number] => 20210217611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => METHODS OF FORMING SILICON NITRIDE [patent_app_type] => utility [patent_app_number] => 17/215958 [patent_app_country] => US [patent_app_date] => 2021-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6272 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17215958 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/215958
Methods of forming silicon nitride including plasma exposure Mar 28, 2021 Issued
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