Search

Javaid H Nasri

Examiner (ID: 15342)

Most Active Art Unit
2839
Art Unit(s)
2833, 2831, 2839
Total Applications
2279
Issued Applications
1975
Pending Applications
35
Abandoned Applications
239

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10568512 [patent_doc_number] => 09291674 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-22 [patent_title] => 'Integrated circuit with low power scan flip-flop' [patent_app_type] => utility [patent_app_number] => 14/580237 [patent_app_country] => US [patent_app_date] => 2014-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7383 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 385 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14580237 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/580237
Integrated circuit with low power scan flip-flop Dec 22, 2014 Issued
Array ( [id] => 10074128 [patent_doc_number] => 09112502 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-18 [patent_title] => 'Voltage controlled switching element gate drive circuit' [patent_app_type] => utility [patent_app_number] => 14/578945 [patent_app_country] => US [patent_app_date] => 2014-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 29 [patent_no_of_words] => 7767 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14578945 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/578945
Voltage controlled switching element gate drive circuit Dec 21, 2014 Issued
Array ( [id] => 12102608 [patent_doc_number] => 09859713 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-02 [patent_title] => 'Parallel inverters connected to one inductor' [patent_app_type] => utility [patent_app_number] => 14/575025 [patent_app_country] => US [patent_app_date] => 2014-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4293 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14575025 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/575025
Parallel inverters connected to one inductor Dec 17, 2014 Issued
Array ( [id] => 11240476 [patent_doc_number] => 09467125 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-11 [patent_title] => 'CMOS Schmitt trigger circuit and associated methods' [patent_app_type] => utility [patent_app_number] => 14/573129 [patent_app_country] => US [patent_app_date] => 2014-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2721 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14573129 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/573129
CMOS Schmitt trigger circuit and associated methods Dec 16, 2014 Issued
Array ( [id] => 10441201 [patent_doc_number] => 20150326213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'APPARATUSES AND METHODS FOR TIMING DOMAIN CROSSING' [patent_app_type] => utility [patent_app_number] => 14/573215 [patent_app_country] => US [patent_app_date] => 2014-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5665 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14573215 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/573215
Apparatuses and methods for timing domain crossing Dec 16, 2014 Issued
Array ( [id] => 10639090 [patent_doc_number] => 09356605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-31 [patent_title] => 'Period measuring circuit and semiconductor device including the same' [patent_app_type] => utility [patent_app_number] => 14/572254 [patent_app_country] => US [patent_app_date] => 2014-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6932 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14572254 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/572254
Period measuring circuit and semiconductor device including the same Dec 15, 2014 Issued
Array ( [id] => 11811926 [patent_doc_number] => 09716505 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-25 [patent_title] => 'System and method for enhanced clocking operation' [patent_app_type] => utility [patent_app_number] => 14/570946 [patent_app_country] => US [patent_app_date] => 2014-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 9359 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14570946 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/570946
System and method for enhanced clocking operation Dec 14, 2014 Issued
Array ( [id] => 11412380 [patent_doc_number] => 09559700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-31 [patent_title] => 'Electronic device and electronic system including the same' [patent_app_type] => utility [patent_app_number] => 14/569263 [patent_app_country] => US [patent_app_date] => 2014-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 11445 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14569263 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/569263
Electronic device and electronic system including the same Dec 11, 2014 Issued
Array ( [id] => 10719076 [patent_doc_number] => 20160065223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'FOREGROUND AND BACKGROUND BANDWIDTH CALIBRATION TECHNIQUES FOR PHASE-LOCKED LOOPS' [patent_app_type] => utility [patent_app_number] => 14/566847 [patent_app_country] => US [patent_app_date] => 2014-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9981 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14566847 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/566847
Foreground and background bandwidth calibration techniques for phase-locked loops Dec 10, 2014 Issued
Array ( [id] => 10697579 [patent_doc_number] => 20160043726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-11 [patent_title] => 'TEST CIRCUIT AND TEST METHOD OF SEMICONDUCTOR APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/564296 [patent_app_country] => US [patent_app_date] => 2014-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7052 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14564296 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/564296
Test circuit and test method of semiconductor apparatus Dec 8, 2014 Issued
Array ( [id] => 11280365 [patent_doc_number] => 09496852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-15 [patent_title] => 'Digital current sensing in power controller' [patent_app_type] => utility [patent_app_number] => 14/560073 [patent_app_country] => US [patent_app_date] => 2014-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9398 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14560073 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/560073
Digital current sensing in power controller Dec 3, 2014 Issued
Array ( [id] => 9928986 [patent_doc_number] => 20150077178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-19 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/555237 [patent_app_country] => US [patent_app_date] => 2014-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4151 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14555237 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/555237
SEMICONDUCTOR DEVICE Nov 25, 2014 Abandoned
Array ( [id] => 12250775 [patent_doc_number] => 09923565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-20 [patent_title] => 'Differential phase-frequency detector' [patent_app_type] => utility [patent_app_number] => 14/547206 [patent_app_country] => US [patent_app_date] => 2014-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3584 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14547206 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/547206
Differential phase-frequency detector Nov 18, 2014 Issued
Array ( [id] => 10351696 [patent_doc_number] => 20150236701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-20 [patent_title] => 'Clock Dividing Device' [patent_app_type] => utility [patent_app_number] => 14/543921 [patent_app_country] => US [patent_app_date] => 2014-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5913 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14543921 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/543921
Clock dividing device Nov 17, 2014 Issued
Array ( [id] => 11179369 [patent_doc_number] => 09411361 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-09 [patent_title] => 'Frequency division clock alignment using pattern selection' [patent_app_type] => utility [patent_app_number] => 14/542216 [patent_app_country] => US [patent_app_date] => 2014-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4956 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14542216 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/542216
Frequency division clock alignment using pattern selection Nov 13, 2014 Issued
Array ( [id] => 10795908 [patent_doc_number] => 20160142066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'FREQUENCY DIVISION CLOCK ALIGNMENT' [patent_app_type] => utility [patent_app_number] => 14/542039 [patent_app_country] => US [patent_app_date] => 2014-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5055 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14542039 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/542039
Frequency division clock alignment Nov 13, 2014 Issued
Array ( [id] => 10277920 [patent_doc_number] => 20150162917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-11 [patent_title] => 'CLOCK GENERATION CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/539293 [patent_app_country] => US [patent_app_date] => 2014-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7040 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14539293 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/539293
Clock generation circuit Nov 11, 2014 Issued
Array ( [id] => 10531824 [patent_doc_number] => 09257973 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-02-09 [patent_title] => 'Supply-state-enabled level shifter interface circuit and method' [patent_app_type] => utility [patent_app_number] => 14/532151 [patent_app_country] => US [patent_app_date] => 2014-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9027 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14532151 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/532151
Supply-state-enabled level shifter interface circuit and method Nov 3, 2014 Issued
Array ( [id] => 11776748 [patent_doc_number] => 09385733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-05 [patent_title] => 'Clock generating apparatus and fractional frequency divider thereof' [patent_app_type] => utility [patent_app_number] => 14/527779 [patent_app_country] => US [patent_app_date] => 2014-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6263 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14527779 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/527779
Clock generating apparatus and fractional frequency divider thereof Oct 29, 2014 Issued
Array ( [id] => 10158387 [patent_doc_number] => 09190170 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-11-17 [patent_title] => 'Shift register unit, gate driving device, display panel and display device' [patent_app_type] => utility [patent_app_number] => 14/525160 [patent_app_country] => US [patent_app_date] => 2014-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 11617 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14525160 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/525160
Shift register unit, gate driving device, display panel and display device Oct 26, 2014 Issued
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