Javaid H Nasri

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Array ( [id] => 8500216 [patent_doc_number] => 20120299624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-29 [patent_title] => 'VOLTAGE CONTROLLED SWITCHING ELEMENT GATE DRIVE CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/480441 [patent_app_country] => US [patent_app_date] => 2012-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7724 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13480441 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8391342 [patent_doc_number] => 20120229186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-13 [patent_title] => 'MEMORY INTERFACE CIRCUIT AND DRIVE CAPABILITY ADJUSTMENT METHOD FOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/474154 [patent_app_country] => US [patent_app_date] => 2012-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8913 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13474154 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8705906 [patent_doc_number] => 20130063195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-14 [patent_title] => 'DIGITAL INPUT BUFFER' [patent_app_type] => utility [patent_app_number] => 13/467256 [patent_app_country] => US [patent_app_date] => 2012-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7776 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13467256 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9118798 [patent_doc_number] => 20130285720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'MULTIPLE CHANNEL PHASE DETECTION' [patent_app_type] => utility [patent_app_number] => 13/456574 [patent_app_country] => US [patent_app_date] => 2012-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3025 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13456574 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9928970 [patent_doc_number] => 20150077163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-19 [patent_title] => 'DYNAMIC FREQUENCY DIVIDER CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/394116 [patent_app_country] => US [patent_app_date] => 2012-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4924 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14394116 [rel_patent_id] =>[rel_patent_doc_number] =>)

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Array ( [id] => 8310968 [patent_doc_number] => 20120187993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-26 [patent_title] => 'Semiconductor Integrated Circuit and Control Method for Clock Signal Synchronization' [patent_app_type] => utility [patent_app_number] => 13/438050 [patent_app_country] => US [patent_app_date] => 2012-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 18891 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13438050 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9065737 [patent_doc_number] => 20130257493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'LATCH WITH A FEEDBACK CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/436106 [patent_app_country] => US [patent_app_date] => 2012-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7026 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13436106 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8288835 [patent_doc_number] => 20120177162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-12 [patent_title] => 'Symmetric Phase Detector' [patent_app_type] => utility [patent_app_number] => 13/424728 [patent_app_country] => US [patent_app_date] => 2012-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4559 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13424728 [rel_patent_id] =>[rel_patent_doc_number] =>)

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