Javaid H Nasri
Examiner (ID: 15342)
Most Active Art Unit | 2839 |
Art Unit(s) | 2833, 2831, 2839 |
Total Applications | 2279 |
Issued Applications | 1975 |
Pending Applications | 35 |
Abandoned Applications | 239 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 7707363
[patent_doc_number] => 20120001664
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-01-05
[patent_title] => 'CLOCK DIVIDER CIRCUIT AND SYSTEM LSI HAVING SAME'
[patent_app_type] => utility
[patent_app_number] => 13/168378
[patent_app_country] => US
[patent_app_date] => 2011-06-24
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13168378
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Array
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[patent_kind] => A1
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[patent_title] => 'CLOCK DIVIDER CIRCUIT AND SYSTEM LSI HAVING SAME'
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Array
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[patent_kind] => A1
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[patent_title] => 'CLOCK DIVIDER CIRCUIT AND SYSTEM LSI HAVING SAME'
[patent_app_type] => utility
[patent_app_number] => 13/168378
[patent_app_country] => US
[patent_app_date] => 2011-06-24
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/168378 | Clock divider circuit and system LSI having same | Jun 23, 2011 | Issued |
Array
(
[id] => 8520341
[patent_doc_number] => 20120319750
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-12-20
[patent_title] => 'MULTI-PART CLOCK MANAGEMENT'
[patent_app_type] => utility
[patent_app_number] => 13/163605
[patent_app_country] => US
[patent_app_date] => 2011-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 4100
[patent_no_of_claims] => 18
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13163605
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/163605 | Multi-part clock management | Jun 16, 2011 | Issued |
Array
(
[id] => 7773762
[patent_doc_number] => 20120038402
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-02-16
[patent_title] => 'Clock generation circuit and electronic apparatus'
[patent_app_type] => utility
[patent_app_number] => 13/067657
[patent_app_country] => US
[patent_app_date] => 2011-06-17
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0038/20120038402.pdf
[firstpage_image] =>[orig_patent_app_number] => 13067657
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/067657 | Clock generation circuit and electronic apparatus | Jun 16, 2011 | Abandoned |
Array
(
[id] => 8514264
[patent_doc_number] => 20120313673
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-12-13
[patent_title] => 'FREQUENCY DIVIDER WITH RETIMED CONTROL SIGNAL AND RELATED FREQUENCY DIVIDING METHOD'
[patent_app_type] => utility
[patent_app_number] => 13/158482
[patent_app_country] => US
[patent_app_date] => 2011-06-13
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13158482
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/158482 | Frequency divider with retimed control signal and related frequency dividing method | Jun 12, 2011 | Issued |
Array
(
[id] => 7660601
[patent_doc_number] => 20110309870
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-12-22
[patent_title] => 'METHOD AND CONFIGURATION FOR GENERATING HIGH-ENERGY MICROWAVE PULSES'
[patent_app_type] => utility
[patent_app_number] => 13/155424
[patent_app_country] => US
[patent_app_date] => 2011-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 2702
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0309/20110309870.pdf
[firstpage_image] =>[orig_patent_app_number] => 13155424
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/155424 | Method and configuration for generating high-energy microwave pulses | Jun 7, 2011 | Issued |
Array
(
[id] => 7796548
[patent_doc_number] => 08125256
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-02-28
[patent_title] => 'Bias generator providing for low power, self-biased delay element and delay line'
[patent_app_type] => utility
[patent_app_number] => 13/152478
[patent_app_country] => US
[patent_app_date] => 2011-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[pdf_file] => patents/08/125/08125256.pdf
[firstpage_image] =>[orig_patent_app_number] => 13152478
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/152478 | Bias generator providing for low power, self-biased delay element and delay line | Jun 2, 2011 | Issued |
Array
(
[id] => 8275500
[patent_doc_number] => 20120169378
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-07-05
[patent_title] => 'DIFFERENTIAL DATA SENSING'
[patent_app_type] => utility
[patent_app_number] => 13/118858
[patent_app_country] => US
[patent_app_date] => 2011-05-31
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/118858 | Differential data sensing | May 30, 2011 | Issued |
Array
(
[id] => 7667329
[patent_doc_number] => 20110316598
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-12-29
[patent_title] => 'APPARATUS AND METHOD FOR MODELING COARSE STEPSIZE DELAY ELEMENT AND DELAY LOCKED LOOP USING SAME'
[patent_app_type] => utility
[patent_app_number] => 13/117934
[patent_app_country] => US
[patent_app_date] => 2011-05-27
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13117934
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/117934 | Apparatus and method for modeling coarse stepsize delay element and delay locked loop using same | May 26, 2011 | Issued |
Array
(
[id] => 8329381
[patent_doc_number] => 08237477
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-08-07
[patent_title] => 'Programmable clock generator used in dynamic-voltage-and-frequency-scaling (DVFS) operated in sub- and near- threshold region'
[patent_app_type] => utility
[patent_app_number] => 13/067232
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13067232
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/067232 | Programmable clock generator used in dynamic-voltage-and-frequency-scaling (DVFS) operated in sub- and near- threshold region | May 17, 2011 | Issued |
Array
(
[id] => 8091131
[patent_doc_number] => 20120081171
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-04-05
[patent_title] => 'SWITCHING DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/108013
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/108013 | Switching device | May 15, 2011 | Issued |
Array
(
[id] => 7739584
[patent_doc_number] => 20120019305
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[patent_title] => 'HARMONIC REJECTION OF SIGNAL CONVERTING DEVICE AND METHOD THEREOF'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/103102 | Harmonic rejection of signal converting device and method thereof | May 7, 2011 | Issued |
Array
(
[id] => 6059456
[patent_doc_number] => 20110199139
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[patent_kind] => A1
[patent_issue_date] => 2011-08-18
[patent_title] => 'FLIP-FLOP CIRCUIT WITH INTERNAL LEVEL SHIFTER'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/097054 | Flip-flop circuit with internal level shifter | Apr 28, 2011 | Issued |
Array
(
[id] => 8474981
[patent_doc_number] => 20120274388
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[patent_issue_date] => 2012-11-01
[patent_title] => 'SWITCHING ELEMENT HAVING AN ELECTROMECHANICAL SWITCH AND METHODS FOR MAKING AND USING SAME'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/097513 | Switching element having an electromechanical switch and methods for making and using same | Apr 28, 2011 | Issued |
Array
(
[id] => 8474970
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[patent_title] => 'SINGLE-TRIGGER LOW-ENERGY FLIP-FLOP CIRCUIT'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/095641 | Single-trigger low-energy flip-flop circuit | Apr 26, 2011 | Issued |
Array
(
[id] => 8029681
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[patent_title] => 'Pulse control device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/091544 | Pulse control device | Apr 20, 2011 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/066731 | Fully differential adaptive bandwidth PLL with differential supply regulation | Apr 20, 2011 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/089859 | Differential current signal circuit | Apr 18, 2011 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/074689 | Robust glitch-free clock switch with an unate clock network | Mar 28, 2011 | Issued |