Javaid H Nasri

Array ( [id] => 7776143 [patent_doc_number] => 08120401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'Methods and systems for digital pulse width modulator' [patent_app_type] => utility [patent_app_number] => 12/622511 [patent_app_country] => US [patent_app_date] => 2009-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4570 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/120/08120401.pdf [firstpage_image] =>[orig_patent_app_number] => 12622511 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7811860 [patent_doc_number] => 08134392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-13 [patent_title] => 'Phase locked loop' [patent_app_type] => utility [patent_app_number] => 12/622604 [patent_app_country] => US [patent_app_date] => 2009-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 35 [patent_no_of_words] => 24667 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 708 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/134/08134392.pdf [firstpage_image] =>[orig_patent_app_number] => 12622604 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6568530 [patent_doc_number] => 20100060347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'BIAS GENERATOR PROVIDING FOR LOW POWER, SELF-BIASED DELAY ELEMENT AND DELAY LINE' [patent_app_type] => utility [patent_app_number] => 12/621983 [patent_app_country] => US [patent_app_date] => 2009-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 15686 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20100060347.pdf [firstpage_image] =>[orig_patent_app_number] => 12621983 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6522286 [patent_doc_number] => 20100123499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-20 [patent_title] => 'INFORMATION SYSTEM, SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 12/619396 [patent_app_country] => US [patent_app_date] => 2009-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4924 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20100123499.pdf [firstpage_image] =>[orig_patent_app_number] => 12619396 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6011472 [patent_doc_number] => 20110221476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => ' PHASE FREQUENCY DETECTOR' [patent_app_type] => utility [patent_app_number] => 13/130518 [patent_app_country] => US [patent_app_date] => 2009-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3112 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20110221476.pdf [firstpage_image] =>[orig_patent_app_number] => 13130518 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5949563 [patent_doc_number] => 20110032011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-10 [patent_title] => 'AUTO FREQUENCY CALIBRATOR, METHOD THEREOF AND FREQUENCY SYNTHESIZER USING IT' [patent_app_type] => utility [patent_app_number] => 12/617151 [patent_app_country] => US [patent_app_date] => 2009-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4358 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20110032011.pdf [firstpage_image] =>[orig_patent_app_number] => 12617151 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4451790 [patent_doc_number] => 07965115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Soft reference switch for phase locked loop' [patent_app_type] => utility [patent_app_number] => 12/617347 [patent_app_country] => US [patent_app_date] => 2009-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1961 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/965/07965115.pdf [firstpage_image] =>[orig_patent_app_number] => 12617347 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8190713 [patent_doc_number] => 08183899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-22 [patent_title] => 'Semiconductor integrated circuit and control method for clock signal synchronization' [patent_app_type] => utility [patent_app_number] => 12/615607 [patent_app_country] => US [patent_app_date] => 2009-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 39 [patent_no_of_words] => 18858 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/183/08183899.pdf [firstpage_image] =>[orig_patent_app_number] => 12615607 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6475161 [patent_doc_number] => 20100207671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-19 [patent_title] => 'FREQUENCY DIVIDING CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/614508 [patent_app_country] => US [patent_app_date] => 2009-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2808 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20100207671.pdf [firstpage_image] =>[orig_patent_app_number] => 12614508 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6052996 [patent_doc_number] => 20110109356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'APERTURE GENERATING CIRCUIT FOR A MULTIPLYING DELAY-LOCKED LOOP' [patent_app_type] => utility [patent_app_number] => 12/613936 [patent_app_country] => US [patent_app_date] => 2009-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4489 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20110109356.pdf [firstpage_image] =>[orig_patent_app_number] => 12613936 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7796546 [patent_doc_number] => 08125254 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-02-28 [patent_title] => 'Techniques for configuring multi-path feedback loops' [patent_app_type] => utility [patent_app_number] => 12/613465 [patent_app_country] => US [patent_app_date] => 2009-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6072 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/125/08125254.pdf [firstpage_image] =>[orig_patent_app_number] => 12613465 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7796545 [patent_doc_number] => 08125253 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-28 [patent_title] => 'System and method for dynamically switching between low and high frequency reference clock to PLL and minimizing PLL output frequency changes' [patent_app_type] => utility [patent_app_number] => 12/610438 [patent_app_country] => US [patent_app_date] => 2009-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 16645 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/125/08125253.pdf [firstpage_image] =>[orig_patent_app_number] => 12610438 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6522223 [patent_doc_number] => 20100123492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-20 [patent_title] => 'CONTROL APPARATUS AND CLOCK SYNCHRONIZING METHOD' [patent_app_type] => utility [patent_app_number] => 12/609460 [patent_app_country] => US [patent_app_date] => 2009-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6283 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20100123492.pdf [firstpage_image] =>[orig_patent_app_number] => 12609460 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5941412 [patent_doc_number] => 20110102032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-05 [patent_title] => 'LOOP FILTER' [patent_app_type] => utility [patent_app_number] => 12/608788 [patent_app_country] => US [patent_app_date] => 2009-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4230 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20110102032.pdf [firstpage_image] =>[orig_patent_app_number] => 12608788 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5981226 [patent_doc_number] => 20110095794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-28 [patent_title] => 'Enhancement of Power Management Using Dynamic Voltage and Frequency Scaling and Digital Phase Lock Loop High Speed Bypass Mode' [patent_app_type] => utility [patent_app_number] => 12/607981 [patent_app_country] => US [patent_app_date] => 2009-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7127 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20110095794.pdf [firstpage_image] =>[orig_patent_app_number] => 12607981 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7713920 [patent_doc_number] => 08093933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-10 [patent_title] => 'Method of fast tracking and jitter improvement in asynchronous sample rate conversion' [patent_app_type] => utility [patent_app_number] => 12/606195 [patent_app_country] => US [patent_app_date] => 2009-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6960 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/093/08093933.pdf [firstpage_image] =>[orig_patent_app_number] => 12606195 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6605871 [patent_doc_number] => 20100033222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-11 [patent_title] => 'PULSE CONTROL DEVICE' [patent_app_type] => utility [patent_app_number] => 12/579705 [patent_app_country] => US [patent_app_date] => 2009-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3994 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20100033222.pdf [firstpage_image] =>[orig_patent_app_number] => 12579705 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7559391 [patent_doc_number] => 20110273223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-10 [patent_title] => 'SIGNAL DISTRIBUTION DEVICE AND DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/144464 [patent_app_country] => US [patent_app_date] => 2009-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11937 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20110273223.pdf [firstpage_image] =>[orig_patent_app_number] => 13144464 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7541069 [patent_doc_number] => 08058915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-15 [patent_title] => 'Digital phase-locked loop and digital phase-frequency detector thereof' [patent_app_type] => utility [patent_app_number] => 12/550393 [patent_app_country] => US [patent_app_date] => 2009-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6085 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/058/08058915.pdf [firstpage_image] =>[orig_patent_app_number] => 12550393 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5964522 [patent_doc_number] => 20110148467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'PHASE-DETECTOR FOR DETECTING PHASE DIFFERENCE OF [PI]2N' [patent_app_type] => utility [patent_app_number] => 13/060914 [patent_app_country] => US [patent_app_date] => 2009-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7431 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20110148467.pdf [firstpage_image] =>[orig_patent_app_number] => 13060914 [rel_patent_id] =>[rel_patent_doc_number] =>)