Javaid H Nasri

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Array ( [id] => 5163568 [patent_doc_number] => 20070285152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'POWER SUPPLY VOLTAGE CONTROLLING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/758343 [patent_app_country] => US [patent_app_date] => 2007-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6311 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20070285152.pdf [firstpage_image] =>[orig_patent_app_number] => 11758343 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 217691 [patent_doc_number] => 07612603 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-11-03 [patent_title] => 'Switching frequency control of switched capacitor circuit using output voltage droop' [patent_app_type] => utility [patent_app_number] => 11/758513 [patent_app_country] => US [patent_app_date] => 2007-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2973 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/612/07612603.pdf [firstpage_image] =>[orig_patent_app_number] => 11758513 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4737695 [patent_doc_number] => 20080231347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'CHARGE PUMP CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/758015 [patent_app_country] => US [patent_app_date] => 2007-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5323 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20080231347.pdf [firstpage_image] =>[orig_patent_app_number] => 11758015 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6414607 [patent_doc_number] => 20100141331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'METHOD OF FORMING A CHARGE PUMP CONTROLLER AND STRUCTURE THEREFOR' [patent_app_type] => utility [patent_app_number] => 11/996475 [patent_app_country] => US [patent_app_date] => 2007-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4265 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20100141331.pdf [firstpage_image] =>[orig_patent_app_number] => 11996475 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5089490 [patent_doc_number] => 20070229129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'PLL CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/691182 [patent_app_country] => US [patent_app_date] => 2007-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5269 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20070229129.pdf [firstpage_image] =>[orig_patent_app_number] => 11691182 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5401723 [patent_doc_number] => 20090237036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'FREQUENCY SYNTHESIZER AND LOOP FILTER USED THEREIN' [patent_app_type] => utility [patent_app_number] => 12/375803 [patent_app_country] => US [patent_app_date] => 2007-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3902 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20090237036.pdf [firstpage_image] =>[orig_patent_app_number] => 12375803 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 331041 [patent_doc_number] => 07511540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-31 [patent_title] => 'Driver circuit for providing an output signal' [patent_app_type] => utility [patent_app_number] => 11/689163 [patent_app_country] => US [patent_app_date] => 2007-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 7740 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/511/07511540.pdf [firstpage_image] =>[orig_patent_app_number] => 11689163 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5257221 [patent_doc_number] => 20070210853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY USING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/685382 [patent_app_country] => US [patent_app_date] => 2007-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 15450 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20070210853.pdf [firstpage_image] =>[orig_patent_app_number] => 11685382 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4769340 [patent_doc_number] => 20080054998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'HALF BRIDGE DRIVER INPUT FILTER' [patent_app_type] => utility [patent_app_number] => 11/684305 [patent_app_country] => US [patent_app_date] => 2007-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1105 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20080054998.pdf [firstpage_image] =>[orig_patent_app_number] => 11684305 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 274796 [patent_doc_number] => 07560963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-14 [patent_title] => 'Delay-locked loop apparatus and delay-locked method' [patent_app_type] => utility [patent_app_number] => 11/683500 [patent_app_country] => US [patent_app_date] => 2007-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 9392 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/560/07560963.pdf [firstpage_image] =>[orig_patent_app_number] => 11683500 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5257211 [patent_doc_number] => 20070210843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'DLL CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/682662 [patent_app_country] => US [patent_app_date] => 2007-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6572 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20070210843.pdf [firstpage_image] =>[orig_patent_app_number] => 11682662 [rel_patent_id] =>[rel_patent_doc_number] =>)

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Array ( [id] => 349372 [patent_doc_number] => 07495491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-24 [patent_title] => 'Inverter based duty cycle correction apparatuses and systems' [patent_app_type] => utility [patent_app_number] => 11/680614 [patent_app_country] => US [patent_app_date] => 2007-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5835 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/495/07495491.pdf [firstpage_image] =>[orig_patent_app_number] => 11680614 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4578466 [patent_doc_number] => 07830186 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-09 [patent_title] => 'Delay locked loop apparatus' [patent_app_type] => utility [patent_app_number] => 11/677619 [patent_app_country] => US [patent_app_date] => 2007-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4763 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/830/07830186.pdf [firstpage_image] =>[orig_patent_app_number] => 11677619 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4871165 [patent_doc_number] => 20080197899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'Trimmable Delay Locked Loop Circuitry with Improved Initialization Characteristics' [patent_app_type] => utility [patent_app_number] => 11/676854 [patent_app_country] => US [patent_app_date] => 2007-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4038 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20080197899.pdf [firstpage_image] =>[orig_patent_app_number] => 11676854 [rel_patent_id] =>[rel_patent_doc_number] =>)

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Array ( [id] => 191507 [patent_doc_number] => 07642821 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-05 [patent_title] => 'Method for synchronizing a clock signal with a reference signal, and phase locked loop' [patent_app_type] => utility [patent_app_number] => 11/675191 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2403 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/642/07642821.pdf [firstpage_image] =>[orig_patent_app_number] => 11675191 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5129424 [patent_doc_number] => 20070205821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-06 [patent_title] => 'INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/673847 [patent_app_country] => US [patent_app_date] => 2007-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1514 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20070205821.pdf [firstpage_image] =>[orig_patent_app_number] => 11673847 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4811127 [patent_doc_number] => 20080191758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'AUTOMATIC BIAS ADJUSTMENT FOR PHASE-LOCKED LOOP CHARGE PUMP' [patent_app_type] => utility [patent_app_number] => 11/672611 [patent_app_country] => US [patent_app_date] => 2007-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6987 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20080191758.pdf [firstpage_image] =>[orig_patent_app_number] => 11672611 [rel_patent_id] =>[rel_patent_doc_number] =>)