Search

Javaid H. Nasri

Examiner (ID: 5819, Phone: (571)272-2095 , Office: P/2831 )

Most Active Art Unit
2839
Art Unit(s)
2839, 2831, 2833
Total Applications
2279
Issued Applications
1981
Pending Applications
35
Abandoned Applications
269

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19913708 [patent_doc_number] => 12289942 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => Optical element, infrared sensor, solid-state imaging element, and manufacturing method for optical element [patent_app_type] => utility [patent_app_number] => 17/874234 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10088 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874234 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/874234
Optical element, infrared sensor, solid-state imaging element, and manufacturing method for optical element Jul 25, 2022 Issued
Array ( [id] => 18008418 [patent_doc_number] => 20220367185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => METHODS FOR SELECTIVELY FORMING A TARGET FILM ON A SUBSTRATE COMPRISING A FIRST DIELECTRIC SURFACE AND A SECOND METALIC SURFACE [patent_app_type] => utility [patent_app_number] => 17/873369 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12708 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873369 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/873369
Methods for selectively forming a target film on a substrate comprising a first dielectric surface and a second metallic surface Jul 25, 2022 Issued
Array ( [id] => 20245947 [patent_doc_number] => 12426292 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Semiconductor device with tunable threshold voltage and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/865846 [patent_app_country] => US [patent_app_date] => 2022-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 30 [patent_no_of_words] => 10655 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17865846 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/865846
Semiconductor device with tunable threshold voltage and method for manufacturing the same Jul 14, 2022 Issued
Array ( [id] => 17963829 [patent_doc_number] => 20220344410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING DETECTION ELECTRODES APPLICABLE FOR A TOUCH SENSOR [patent_app_type] => utility [patent_app_number] => 17/862926 [patent_app_country] => US [patent_app_date] => 2022-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8014 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17862926 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/862926
Semiconductor device including detection electrodes applicable for a touch sensor Jul 11, 2022 Issued
Array ( [id] => 20455909 [patent_doc_number] => 12518969 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => Semiconductor structure having reliable line pattern designs and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/811080 [patent_app_country] => US [patent_app_date] => 2022-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 1753 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17811080 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/811080
Semiconductor structure having reliable line pattern designs and method of manufacturing the same Jul 6, 2022 Issued
Array ( [id] => 18882892 [patent_doc_number] => 20240006261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => PACKAGE HEATERS FOR COLD TEMPERATURE OPERATION AND METHOD [patent_app_type] => utility [patent_app_number] => 17/855176 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3874 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17855176 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/855176
PACKAGE HEATERS FOR COLD TEMPERATURE OPERATION AND METHOD Jun 29, 2022 Pending
Array ( [id] => 17949363 [patent_doc_number] => 20220336382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => SEMICONDUCTOR PACKAGE DEVICE WITH INTEGRATED INDUCTOR AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/808997 [patent_app_country] => US [patent_app_date] => 2022-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6855 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17808997 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/808997
Semiconductor package device with integrated inductor and manufacturing method thereof Jun 25, 2022 Issued
Array ( [id] => 18857291 [patent_doc_number] => 11854886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Methods of TSV formation for advanced packaging [patent_app_type] => utility [patent_app_number] => 17/847419 [patent_app_country] => US [patent_app_date] => 2022-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 32 [patent_no_of_words] => 6621 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17847419 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/847419
Methods of TSV formation for advanced packaging Jun 22, 2022 Issued
Array ( [id] => 20566231 [patent_doc_number] => 12568858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-03 [patent_title] => Secondary die with a ground plane for strip line routing [patent_app_type] => utility [patent_app_number] => 17/845835 [patent_app_country] => US [patent_app_date] => 2022-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3339 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17845835 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/845835
Secondary die with a ground plane for strip line routing Jun 20, 2022 Issued
Array ( [id] => 20189847 [patent_doc_number] => 12400972 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Semiconductor device for suppressing excessive wetting and spreading of bonding layer [patent_app_type] => utility [patent_app_number] => 17/843319 [patent_app_country] => US [patent_app_date] => 2022-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 3417 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17843319 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/843319
Semiconductor device for suppressing excessive wetting and spreading of bonding layer Jun 16, 2022 Issued
Array ( [id] => 18833851 [patent_doc_number] => 20230402378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => HIGH ASPECT RATIO BURIED POWER RAIL METALLIZATION [patent_app_type] => utility [patent_app_number] => 17/806570 [patent_app_country] => US [patent_app_date] => 2022-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10197 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17806570 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/806570
High aspect ratio buried power rail metallization Jun 12, 2022 Issued
Array ( [id] => 19539545 [patent_doc_number] => 12132102 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-29 [patent_title] => Enhanced cascade field effect transistor [patent_app_type] => utility [patent_app_number] => 17/838485 [patent_app_country] => US [patent_app_date] => 2022-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5279 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17838485 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/838485
Enhanced cascade field effect transistor Jun 12, 2022 Issued
Array ( [id] => 17886557 [patent_doc_number] => 20220302035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => SEMICONDUCTOR PACKAGE WITH INTERPOSER [patent_app_type] => utility [patent_app_number] => 17/835768 [patent_app_country] => US [patent_app_date] => 2022-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7435 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17835768 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/835768
Methods of manufacturing semiconductor packages Jun 7, 2022 Issued
Array ( [id] => 19610941 [patent_doc_number] => 12159822 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-03 [patent_title] => Method of manufacturing a semiconductor package having conductive pillars [patent_app_type] => utility [patent_app_number] => 17/805594 [patent_app_country] => US [patent_app_date] => 2022-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 11285 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17805594 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/805594
Method of manufacturing a semiconductor package having conductive pillars Jun 5, 2022 Issued
Array ( [id] => 20259066 [patent_doc_number] => 12431431 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Conductive structure interconnects with downward projections [patent_app_type] => utility [patent_app_number] => 17/804919 [patent_app_country] => US [patent_app_date] => 2022-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 7737 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17804919 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/804919
Conductive structure interconnects with downward projections May 31, 2022 Issued
Array ( [id] => 19444692 [patent_doc_number] => 12094984 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/825359 [patent_app_country] => US [patent_app_date] => 2022-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 32 [patent_no_of_words] => 6429 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17825359 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/825359
Semiconductor device May 25, 2022 Issued
Array ( [id] => 20082582 [patent_doc_number] => 12356682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Semiconductor structure with conductive structure [patent_app_type] => utility [patent_app_number] => 17/749359 [patent_app_country] => US [patent_app_date] => 2022-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 54 [patent_no_of_words] => 4189 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17749359 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/749359
Semiconductor structure with conductive structure May 19, 2022 Issued
Array ( [id] => 18789279 [patent_doc_number] => 20230377929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => ALIGNMENT TARGETS ON OPPOSING SUBSTRATE SIDES [patent_app_type] => utility [patent_app_number] => 17/663858 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6478 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17663858 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/663858
Alignment of targets on opposite sides of a substrate May 17, 2022 Issued
Array ( [id] => 17810905 [patent_doc_number] => 20220262740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => ELECTRONIC ASSEMBLY, ELECTRONIC APPARATUS INCLUDING THE SAME AND METHOD FOR FABRICATING ELECTRONIC ASSEMBLY [patent_app_type] => utility [patent_app_number] => 17/737285 [patent_app_country] => US [patent_app_date] => 2022-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8665 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17737285 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/737285
Method for fabricating electronic assembly including a magnetic field shielding film May 4, 2022 Issued
Array ( [id] => 17993314 [patent_doc_number] => 20220359351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => MICROELECTRONICS PACKAGE ASSEMBLIES AND PROCESSES FOR MAKING [patent_app_type] => utility [patent_app_number] => 17/737564 [patent_app_country] => US [patent_app_date] => 2022-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17889 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17737564 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/737564
Microelectronics package assemblies and processes for making May 4, 2022 Issued
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